1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MCE_PRIVATE_H 8*91f16700Schasinglulu #define MCE_PRIVATE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdbool.h> 11*91f16700Schasinglulu #include <tegra_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /******************************************************************************* 14*91f16700Schasinglulu * Macros to prepare CSTATE info request 15*91f16700Schasinglulu ******************************************************************************/ 16*91f16700Schasinglulu /* Description of the parameters for UPDATE_CSTATE_INFO request */ 17*91f16700Schasinglulu #define CLUSTER_CSTATE_MASK 0x7U 18*91f16700Schasinglulu #define CLUSTER_CSTATE_SHIFT 0X0U 19*91f16700Schasinglulu #define CLUSTER_CSTATE_UPDATE_BIT (1U << 7) 20*91f16700Schasinglulu #define CCPLEX_CSTATE_MASK 0x7U 21*91f16700Schasinglulu #define CCPLEX_CSTATE_SHIFT 8U 22*91f16700Schasinglulu #define CCPLEX_CSTATE_UPDATE_BIT (1U << 15) 23*91f16700Schasinglulu #define SYSTEM_CSTATE_MASK 0xFU 24*91f16700Schasinglulu #define SYSTEM_CSTATE_SHIFT 16U 25*91f16700Schasinglulu #define SYSTEM_CSTATE_UPDATE_BIT (1U << 23) 26*91f16700Schasinglulu #define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31) 27*91f16700Schasinglulu #define CSTATE_WAKE_MASK_SHIFT 32U 28*91f16700Schasinglulu #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU 29*91f16700Schasinglulu 30*91f16700Schasinglulu /******************************************************************************* 31*91f16700Schasinglulu * Core ID mask (bits 3:0 in the online request) 32*91f16700Schasinglulu ******************************************************************************/ 33*91f16700Schasinglulu #define MCE_CORE_ID_MASK 0xFU 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * C-state statistics macros 37*91f16700Schasinglulu ******************************************************************************/ 38*91f16700Schasinglulu #define MCE_STAT_ID_SHIFT 16U 39*91f16700Schasinglulu 40*91f16700Schasinglulu /******************************************************************************* 41*91f16700Schasinglulu * Security config macros 42*91f16700Schasinglulu ******************************************************************************/ 43*91f16700Schasinglulu #define STRICT_CHECKING_ENABLED_SET (1UL << 0) 44*91f16700Schasinglulu #define STRICT_CHECKING_LOCKED_SET (1UL << 1) 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* declarations for NVG handler functions */ 47*91f16700Schasinglulu uint64_t nvg_get_version(void); 48*91f16700Schasinglulu void nvg_set_wake_time(uint32_t wake_time); 49*91f16700Schasinglulu void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, 50*91f16700Schasinglulu uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask); 51*91f16700Schasinglulu int32_t nvg_set_cstate_stat_query_value(uint64_t data); 52*91f16700Schasinglulu uint64_t nvg_get_cstate_stat_query_value(void); 53*91f16700Schasinglulu int32_t nvg_is_sc7_allowed(void); 54*91f16700Schasinglulu int32_t nvg_online_core(uint32_t core); 55*91f16700Schasinglulu int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx); 56*91f16700Schasinglulu int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time); 57*91f16700Schasinglulu int32_t nvg_roc_clean_cache_trbits(void); 58*91f16700Schasinglulu void nvg_enable_strict_checking_mode(void); 59*91f16700Schasinglulu void nvg_verify_strict_checking_mode(void); 60*91f16700Schasinglulu void nvg_system_shutdown(void); 61*91f16700Schasinglulu void nvg_system_reboot(void); 62*91f16700Schasinglulu void nvg_clear_hsm_corr_status(void); 63*91f16700Schasinglulu 64*91f16700Schasinglulu /* declarations for assembly functions */ 65*91f16700Schasinglulu void nvg_set_request_data(uint64_t req, uint64_t data); 66*91f16700Schasinglulu void nvg_set_request(uint64_t req); 67*91f16700Schasinglulu uint64_t nvg_get_result(void); 68*91f16700Schasinglulu uint64_t nvg_cache_clean(void); 69*91f16700Schasinglulu uint64_t nvg_cache_clean_inval(void); 70*91f16700Schasinglulu uint64_t nvg_cache_inval_all(void); 71*91f16700Schasinglulu 72*91f16700Schasinglulu /* MCE helper functions */ 73*91f16700Schasinglulu void mce_enable_strict_checking(void); 74*91f16700Schasinglulu void mce_verify_strict_checking(void); 75*91f16700Schasinglulu void mce_system_shutdown(void); 76*91f16700Schasinglulu void mce_system_reboot(void); 77*91f16700Schasinglulu void mce_clear_hsm_corr_status(void); 78*91f16700Schasinglulu 79*91f16700Schasinglulu #endif /* MCE_PRIVATE_H */ 80