1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu# Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu# 5*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu# 7*91f16700Schasinglulu 8*91f16700Schasinglulu# platform configs 9*91f16700SchasingluluENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1 10*91f16700Schasinglulu$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) 11*91f16700Schasinglulu 12*91f16700SchasingluluENABLE_CHIP_VERIFICATION_HARNESS := 0 13*91f16700Schasinglulu$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS)) 14*91f16700Schasinglulu 15*91f16700SchasingluluRESET_TO_BL31 := 1 16*91f16700Schasinglulu 17*91f16700SchasingluluPROGRAMMABLE_RESET_ADDRESS := 0 18*91f16700Schasinglulu 19*91f16700SchasingluluCOLD_BOOT_SINGLE_CPU := 1 20*91f16700Schasinglulu 21*91f16700SchasingluluRELOCATE_BL32_IMAGE := 1 22*91f16700Schasinglulu 23*91f16700Schasinglulu# platform settings 24*91f16700SchasingluluTZDRAM_BASE := 0x30000000 25*91f16700Schasinglulu$(eval $(call add_define,TZDRAM_BASE)) 26*91f16700Schasinglulu 27*91f16700SchasingluluPLATFORM_CLUSTER_COUNT := 2 28*91f16700Schasinglulu$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 29*91f16700Schasinglulu 30*91f16700SchasingluluPLATFORM_MAX_CPUS_PER_CLUSTER := 4 31*91f16700Schasinglulu$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 32*91f16700Schasinglulu 33*91f16700SchasingluluMAX_XLAT_TABLES := 25 34*91f16700Schasinglulu$(eval $(call add_define,MAX_XLAT_TABLES)) 35*91f16700Schasinglulu 36*91f16700SchasingluluMAX_MMAP_REGIONS := 30 37*91f16700Schasinglulu$(eval $(call add_define,MAX_MMAP_REGIONS)) 38*91f16700Schasinglulu 39*91f16700Schasinglulu# platform files 40*91f16700SchasingluluPLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \ 41*91f16700Schasinglulu -I${SOC_DIR}/drivers/include 42*91f16700Schasinglulu 43*91f16700SchasingluluBL31_SOURCES += ${TEGRA_GICv2_SOURCES} \ 44*91f16700Schasinglulu drivers/ti/uart/aarch64/16550_console.S \ 45*91f16700Schasinglulu lib/cpus/aarch64/denver.S \ 46*91f16700Schasinglulu lib/cpus/aarch64/cortex_a57.S \ 47*91f16700Schasinglulu ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \ 48*91f16700Schasinglulu ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \ 49*91f16700Schasinglulu ${TEGRA_DRIVERS}/gpcdma/gpcdma.c \ 50*91f16700Schasinglulu ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \ 51*91f16700Schasinglulu ${TEGRA_DRIVERS}/smmu/smmu.c \ 52*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/mce.c \ 53*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/ari.c \ 54*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/nvg.c \ 55*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 56*91f16700Schasinglulu $(SOC_DIR)/drivers/se/se.c \ 57*91f16700Schasinglulu ${SOC_DIR}/plat_memctrl.c \ 58*91f16700Schasinglulu ${SOC_DIR}/plat_psci_handlers.c \ 59*91f16700Schasinglulu ${SOC_DIR}/plat_setup.c \ 60*91f16700Schasinglulu ${SOC_DIR}/plat_secondary.c \ 61*91f16700Schasinglulu ${SOC_DIR}/plat_sip_calls.c \ 62*91f16700Schasinglulu ${SOC_DIR}/plat_smmu.c \ 63*91f16700Schasinglulu ${SOC_DIR}/plat_trampoline.S 64*91f16700Schasinglulu 65*91f16700Schasinglulu# Enable workarounds for selected Cortex-A57 erratas. 66*91f16700SchasingluluA57_DISABLE_NON_TEMPORAL_HINT := 1 67*91f16700SchasingluluERRATA_A57_806969 := 1 68*91f16700SchasingluluERRATA_A57_813419 := 1 69*91f16700SchasingluluERRATA_A57_813420 := 1 70*91f16700SchasingluluERRATA_A57_826974 := 1 71*91f16700SchasingluluERRATA_A57_826977 := 1 72*91f16700SchasingluluERRATA_A57_828024 := 1 73*91f16700SchasingluluERRATA_A57_829520 := 1 74*91f16700SchasingluluERRATA_A57_833471 := 1 75*91f16700Schasinglulu 76*91f16700Schasinglulu# Enable higher performance Non-cacheable load forwarding 77*91f16700SchasingluluA57_ENABLE_NONCACHEABLE_LOAD_FWD := 1 78