1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu#include <arch.h> 9*91f16700Schasinglulu#include <asm_macros.S> 10*91f16700Schasinglulu#include <common/bl_common.h> 11*91f16700Schasinglulu#include <memctrl_v2.h> 12*91f16700Schasinglulu#include <plat/common/common_def.h> 13*91f16700Schasinglulu#include <tegra_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu#define TEGRA186_MC_CTX_SIZE 0x93 16*91f16700Schasinglulu 17*91f16700Schasinglulu .globl tegra186_get_mc_ctx_size 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* 20*91f16700Schasinglulu * Tegra186 reset data (offset 0x0 - 0x420) 21*91f16700Schasinglulu * 22*91f16700Schasinglulu * 0x000: MC context start 23*91f16700Schasinglulu * 0x420: MC context end 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu 26*91f16700Schasinglulu .align 4 27*91f16700Schasinglulu__tegra186_mc_context: 28*91f16700Schasinglulu .rept TEGRA186_MC_CTX_SIZE 29*91f16700Schasinglulu .quad 0 30*91f16700Schasinglulu .endr 31*91f16700Schasinglulu 32*91f16700Schasinglulu .align 4 33*91f16700Schasinglulu__tegra186_mc_context_end: 34*91f16700Schasinglulu 35*91f16700Schasinglulu/* return the size of the MC context */ 36*91f16700Schasinglulufunc tegra186_get_mc_ctx_size 37*91f16700Schasinglulu adr x0, __tegra186_mc_context_end 38*91f16700Schasinglulu adr x1, __tegra186_mc_context 39*91f16700Schasinglulu sub x0, x0, x1 40*91f16700Schasinglulu ret 41*91f16700Schasingluluendfunc tegra186_get_mc_ctx_size 42