1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <string.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <common/debug.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <mce.h> 15*91f16700Schasinglulu #include <tegra_def.h> 16*91f16700Schasinglulu #include <tegra_private.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U 19*91f16700Schasinglulu #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define CPU_RESET_MODE_AA64 1U 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * Setup secondary CPU vectors 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu void plat_secondary_setup(void) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu uint32_t addr_low, addr_high; 29*91f16700Schasinglulu 30*91f16700Schasinglulu INFO("Setting up secondary CPU boot\n"); 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* TZDRAM base will be used as the "resume" address */ 33*91f16700Schasinglulu addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64; 34*91f16700Schasinglulu addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU); 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* save reset vector to be used during SYSTEM_SUSPEND exit */ 37*91f16700Schasinglulu mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, 38*91f16700Schasinglulu addr_low); 39*91f16700Schasinglulu mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, 40*91f16700Schasinglulu addr_high); 41*91f16700Schasinglulu } 42