1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef TEGRA_PLATFORM_H 9*91f16700Schasinglulu #define TEGRA_PLATFORM_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <cdefs.h> 12*91f16700Schasinglulu #include <lib/utils_def.h> 13*91f16700Schasinglulu #include <stdbool.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * Tegra major, minor version helper macros 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define MAJOR_VERSION_SHIFT U(0x4) 19*91f16700Schasinglulu #define MAJOR_VERSION_MASK U(0xF) 20*91f16700Schasinglulu #define MINOR_VERSION_SHIFT U(0x10) 21*91f16700Schasinglulu #define MINOR_VERSION_MASK U(0xF) 22*91f16700Schasinglulu #define CHIP_ID_SHIFT U(8) 23*91f16700Schasinglulu #define CHIP_ID_MASK U(0xFF) 24*91f16700Schasinglulu #define PRE_SI_PLATFORM_SHIFT U(0x14) 25*91f16700Schasinglulu #define PRE_SI_PLATFORM_MASK U(0xF) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /******************************************************************************* 28*91f16700Schasinglulu * Tegra chip ID values 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu #define TEGRA_CHIPID_TEGRA13 U(0x13) 31*91f16700Schasinglulu #define TEGRA_CHIPID_TEGRA21 U(0x21) 32*91f16700Schasinglulu #define TEGRA_CHIPID_TEGRA18 U(0x18) 33*91f16700Schasinglulu #define TEGRA_CHIPID_TEGRA19 U(0x19) 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * JEDEC Standard Manufacturer's Identification Code and Bank ID 37*91f16700Schasinglulu ******************************************************************************/ 38*91f16700Schasinglulu #define JEDEC_NVIDIA_MFID U(0x6B) 39*91f16700Schasinglulu #define JEDEC_NVIDIA_BKID U(3) 40*91f16700Schasinglulu 41*91f16700Schasinglulu #ifndef __ASSEMBLER__ 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* 44*91f16700Schasinglulu * Tegra chip ID major/minor identifiers 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu uint32_t tegra_get_chipid_major(void); 47*91f16700Schasinglulu uint32_t tegra_get_chipid_minor(void); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* 50*91f16700Schasinglulu * Tegra chip ID identifiers 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu bool tegra_chipid_is_t186(void); 53*91f16700Schasinglulu bool tegra_chipid_is_t210(void); 54*91f16700Schasinglulu bool tegra_chipid_is_t210_b01(void); 55*91f16700Schasinglulu bool tegra_chipid_is_t194(void); 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* 58*91f16700Schasinglulu * Tegra platform identifiers 59*91f16700Schasinglulu */ 60*91f16700Schasinglulu bool tegra_platform_is_silicon(void); 61*91f16700Schasinglulu bool tegra_platform_is_qt(void); 62*91f16700Schasinglulu bool tegra_platform_is_emulation(void); 63*91f16700Schasinglulu bool tegra_platform_is_linsim(void); 64*91f16700Schasinglulu bool tegra_platform_is_fpga(void); 65*91f16700Schasinglulu bool tegra_platform_is_unit_fpga(void); 66*91f16700Schasinglulu bool tegra_platform_is_virt_dev_kit(void); 67*91f16700Schasinglulu 68*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 69*91f16700Schasinglulu 70*91f16700Schasinglulu #endif /* TEGRA_PLATFORM_H */ 71