1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef TEGRA194_PRIVATE_H 8*91f16700Schasinglulu #define TEGRA194_PRIVATE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu void tegra194_cpu_reset_handler(void); 11*91f16700Schasinglulu uint64_t tegra194_get_cpu_reset_handler_base(void); 12*91f16700Schasinglulu uint64_t tegra194_get_cpu_reset_handler_size(void); 13*91f16700Schasinglulu uint64_t tegra194_get_mc_ctx_offset(void); 14*91f16700Schasinglulu void tegra194_set_system_suspend_entry(void); 15*91f16700Schasinglulu 16*91f16700Schasinglulu #endif /* TEGRA194_PRIVATE_H */ 17