1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu#ifndef PLAT_MACROS_S 9*91f16700Schasinglulu#define PLAT_MACROS_S 10*91f16700Schasinglulu 11*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 12*91f16700Schasinglulu#include <tegra_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu.section .rodata.gic_reg_name, "aS" 15*91f16700Schasinglulugicc_regs: 16*91f16700Schasinglulu .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 17*91f16700Schasinglulugicd_pend_reg: 18*91f16700Schasinglulu .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 19*91f16700Schasinglulunewline: 20*91f16700Schasinglulu .asciz "\n" 21*91f16700Schasingluluspacer: 22*91f16700Schasinglulu .asciz ":\t\t0x" 23*91f16700Schasinglulu 24*91f16700Schasinglulu/* --------------------------------------------- 25*91f16700Schasinglulu * The below macro prints out relevant GIC 26*91f16700Schasinglulu * registers whenever an unhandled exception is 27*91f16700Schasinglulu * taken in BL31. 28*91f16700Schasinglulu * --------------------------------------------- 29*91f16700Schasinglulu */ 30*91f16700Schasinglulu.macro plat_crash_print_regs 31*91f16700Schasinglulu#ifdef TEGRA_GICC_BASE 32*91f16700Schasinglulu mov_imm x16, TEGRA_GICC_BASE 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* gicc base address is now in x16 */ 35*91f16700Schasinglulu adr x6, gicc_regs /* Load the gicc reg list to x6 */ 36*91f16700Schasinglulu /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 37*91f16700Schasinglulu ldr w8, [x16, #GICC_HPPIR] 38*91f16700Schasinglulu ldr w9, [x16, #GICC_AHPPIR] 39*91f16700Schasinglulu ldr w10, [x16, #GICC_CTLR] 40*91f16700Schasinglulu /* Store to the crash buf and print to cosole */ 41*91f16700Schasinglulu bl str_in_crash_buf_print 42*91f16700Schasinglulu#endif 43*91f16700Schasinglulu /* Print the GICD_ISPENDR regs */ 44*91f16700Schasinglulu mov_imm x16, TEGRA_GICD_BASE 45*91f16700Schasinglulu add x7, x16, #GICD_ISPENDR 46*91f16700Schasinglulu adr x4, gicd_pend_reg 47*91f16700Schasinglulu bl asm_print_str 48*91f16700Schasinglulu2: 49*91f16700Schasinglulu sub x4, x7, x16 50*91f16700Schasinglulu cmp x4, #0x280 51*91f16700Schasinglulu b.eq 1f 52*91f16700Schasinglulu bl asm_print_hex 53*91f16700Schasinglulu adr x4, spacer 54*91f16700Schasinglulu bl asm_print_str 55*91f16700Schasinglulu ldr w4, [x7], #4 56*91f16700Schasinglulu bl asm_print_hex 57*91f16700Schasinglulu adr x4, newline 58*91f16700Schasinglulu bl asm_print_str 59*91f16700Schasinglulu b 2b 60*91f16700Schasinglulu1: 61*91f16700Schasinglulu.endm 62*91f16700Schasinglulu 63*91f16700Schasinglulu#endif /* PLAT_MACROS_S */ 64