1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef TEGRA_GIC_H 9*91f16700Schasinglulu #define TEGRA_GIC_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <common/interrupt_props.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /******************************************************************************* 14*91f16700Schasinglulu * Per-CPU struct describing FIQ state to be stored 15*91f16700Schasinglulu ******************************************************************************/ 16*91f16700Schasinglulu typedef struct pcpu_fiq_state { 17*91f16700Schasinglulu uint64_t elr_el3; 18*91f16700Schasinglulu uint64_t spsr_el3; 19*91f16700Schasinglulu } pcpu_fiq_state_t; 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * Function declarations 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu void tegra_gic_cpuif_deactivate(void); 25*91f16700Schasinglulu void tegra_gic_init(void); 26*91f16700Schasinglulu void tegra_gic_pcpu_init(void); 27*91f16700Schasinglulu void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 28*91f16700Schasinglulu unsigned int interrupt_props_num); 29*91f16700Schasinglulu 30*91f16700Schasinglulu #endif /* TEGRA_GIC_H */ 31