1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef SMMU_H 9*91f16700Schasinglulu #define SMMU_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <memctrl_v2.h> 14*91f16700Schasinglulu #include <tegra_def.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define SMMU_CBn_ACTLR (0x4U) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * SMMU Global Secure Aux. Configuration Register 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu #define SMMU_GSR0_SECURE_ACR 0x10U 22*91f16700Schasinglulu #define SMMU_GNSR_ACR (SMMU_GSR0_SECURE_ACR + 0x400U) 23*91f16700Schasinglulu #define SMMU_GSR0_PGSIZE_SHIFT 16U 24*91f16700Schasinglulu #define SMMU_GSR0_PGSIZE_4K (0U << SMMU_GSR0_PGSIZE_SHIFT) 25*91f16700Schasinglulu #define SMMU_GSR0_PGSIZE_64K (1U << SMMU_GSR0_PGSIZE_SHIFT) 26*91f16700Schasinglulu #define SMMU_ACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) 27*91f16700Schasinglulu #define SMMU_GSR0_PER (0x20200U) 28*91f16700Schasinglulu 29*91f16700Schasinglulu /******************************************************************************* 30*91f16700Schasinglulu * SMMU Global Aux. Control Register 31*91f16700Schasinglulu ******************************************************************************/ 32*91f16700Schasinglulu #define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* SMMU IDs currently supported by the driver */ 35*91f16700Schasinglulu enum { 36*91f16700Schasinglulu TEGRA_SMMU0 = 0U, 37*91f16700Schasinglulu TEGRA_SMMU1 = 1U, 38*91f16700Schasinglulu TEGRA_SMMU2 = 2U 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu uint32_t ret = 0U; 44*91f16700Schasinglulu 45*91f16700Schasinglulu #if defined(TEGRA_SMMU0_BASE) 46*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU0) { 47*91f16700Schasinglulu ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off); 48*91f16700Schasinglulu } 49*91f16700Schasinglulu #endif 50*91f16700Schasinglulu 51*91f16700Schasinglulu #if defined(TEGRA_SMMU1_BASE) 52*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU1) { 53*91f16700Schasinglulu ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off); 54*91f16700Schasinglulu } 55*91f16700Schasinglulu #endif 56*91f16700Schasinglulu 57*91f16700Schasinglulu #if defined(TEGRA_SMMU2_BASE) 58*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU2) { 59*91f16700Schasinglulu ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off); 60*91f16700Schasinglulu } 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu return ret; 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu static inline void tegra_smmu_write_32(uint32_t smmu_id, 67*91f16700Schasinglulu uint32_t off, uint32_t val) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu #if defined(TEGRA_SMMU0_BASE) 70*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU0) { 71*91f16700Schasinglulu mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val); 72*91f16700Schasinglulu } 73*91f16700Schasinglulu #endif 74*91f16700Schasinglulu 75*91f16700Schasinglulu #if defined(TEGRA_SMMU1_BASE) 76*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU1) { 77*91f16700Schasinglulu mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val); 78*91f16700Schasinglulu } 79*91f16700Schasinglulu #endif 80*91f16700Schasinglulu 81*91f16700Schasinglulu #if defined(TEGRA_SMMU2_BASE) 82*91f16700Schasinglulu if (smmu_id == TEGRA_SMMU2) { 83*91f16700Schasinglulu mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val); 84*91f16700Schasinglulu } 85*91f16700Schasinglulu #endif 86*91f16700Schasinglulu } 87*91f16700Schasinglulu 88*91f16700Schasinglulu void tegra_smmu_init(void); 89*91f16700Schasinglulu void tegra_smmu_verify(void); 90*91f16700Schasinglulu uint32_t plat_get_num_smmu_devices(void); 91*91f16700Schasinglulu 92*91f16700Schasinglulu #endif /* SMMU_H */ 93