1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef SECURITY_ENGINE_H 9*91f16700Schasinglulu #define SECURITY_ENGINE_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu /******************************************************************************* 12*91f16700Schasinglulu * Structure definition 13*91f16700Schasinglulu ******************************************************************************/ 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Security Engine Linked List */ 16*91f16700Schasinglulu struct tegra_se_ll { 17*91f16700Schasinglulu /* DMA buffer address */ 18*91f16700Schasinglulu uint32_t addr; 19*91f16700Schasinglulu /* Data length in DMA buffer */ 20*91f16700Schasinglulu uint32_t data_len; 21*91f16700Schasinglulu }; 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define SE_LL_MAX_BUFFER_NUM 4 24*91f16700Schasinglulu typedef struct tegra_se_io_lst { 25*91f16700Schasinglulu volatile uint32_t last_buff_num; 26*91f16700Schasinglulu volatile struct tegra_se_ll buffer[SE_LL_MAX_BUFFER_NUM]; 27*91f16700Schasinglulu } tegra_se_io_lst_t __attribute__((aligned(4))); 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* SE device structure */ 30*91f16700Schasinglulu typedef struct tegra_se_dev { 31*91f16700Schasinglulu /* Security Engine ID */ 32*91f16700Schasinglulu const int se_num; 33*91f16700Schasinglulu /* SE base address */ 34*91f16700Schasinglulu const uint64_t se_base; 35*91f16700Schasinglulu /* SE context size in AES blocks */ 36*91f16700Schasinglulu const uint32_t ctx_size_blks; 37*91f16700Schasinglulu /* pointer to source linked list buffer */ 38*91f16700Schasinglulu tegra_se_io_lst_t *src_ll_buf; 39*91f16700Schasinglulu /* pointer to destination linked list buffer */ 40*91f16700Schasinglulu tegra_se_io_lst_t *dst_ll_buf; 41*91f16700Schasinglulu /* LP context buffer pointer */ 42*91f16700Schasinglulu uint32_t *ctx_save_buf; 43*91f16700Schasinglulu } tegra_se_dev_t; 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* PKA1 device structure */ 46*91f16700Schasinglulu typedef struct tegra_pka_dev { 47*91f16700Schasinglulu /* PKA1 base address */ 48*91f16700Schasinglulu uint64_t pka_base; 49*91f16700Schasinglulu } tegra_pka_dev_t; 50*91f16700Schasinglulu 51*91f16700Schasinglulu /******************************************************************************* 52*91f16700Schasinglulu * Public interface 53*91f16700Schasinglulu ******************************************************************************/ 54*91f16700Schasinglulu void tegra_se_init(void); 55*91f16700Schasinglulu int tegra_se_suspend(void); 56*91f16700Schasinglulu void tegra_se_resume(void); 57*91f16700Schasinglulu int tegra_se_save_tzram(void); 58*91f16700Schasinglulu int32_t tegra_se_save_sha256_hash(uint64_t bl31_base, uint32_t src_len_inbyte); 59*91f16700Schasinglulu 60*91f16700Schasinglulu #endif /* SECURITY_ENGINE_H */ 61