1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PMC_H 9*91f16700Schasinglulu #define PMC_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu #include <lib/utils_def.h> 13*91f16700Schasinglulu #include <stdbool.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <tegra_def.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define PMC_CONFIG U(0x0) 18*91f16700Schasinglulu #define PMC_IO_DPD_SAMPLE U(0x20) 19*91f16700Schasinglulu #define PMC_DPD_ENABLE_0 U(0x24) 20*91f16700Schasinglulu #define PMC_PWRGATE_STATUS U(0x38) 21*91f16700Schasinglulu #define PMC_PWRGATE_TOGGLE U(0x30) 22*91f16700Schasinglulu #define PMC_SCRATCH1 U(0x54) 23*91f16700Schasinglulu #define PMC_CRYPTO_OP_0 U(0xf4) 24*91f16700Schasinglulu #define PMC_TOGGLE_START U(0x100) 25*91f16700Schasinglulu #define PMC_SCRATCH31 U(0x118) 26*91f16700Schasinglulu #define PMC_SCRATCH32 U(0x11C) 27*91f16700Schasinglulu #define PMC_SCRATCH33 U(0x120) 28*91f16700Schasinglulu #define PMC_SCRATCH39 U(0x138) 29*91f16700Schasinglulu #define PMC_SCRATCH40 U(0x13C) 30*91f16700Schasinglulu #define PMC_SCRATCH41 U(0x140) 31*91f16700Schasinglulu #define PMC_SCRATCH42 U(0x144) 32*91f16700Schasinglulu #define PMC_SCRATCH43 U(0x22C) 33*91f16700Schasinglulu #define PMC_SCRATCH44 U(0x230) 34*91f16700Schasinglulu #define PMC_SCRATCH45 U(0x234) 35*91f16700Schasinglulu #define PMC_SCRATCH46 U(0x238) 36*91f16700Schasinglulu #define PMC_SCRATCH47 U(0x23C) 37*91f16700Schasinglulu #define PMC_SCRATCH48 U(0x240) 38*91f16700Schasinglulu #define PMC_SCRATCH50 U(0x248) 39*91f16700Schasinglulu #define PMC_SCRATCH51 U(0x24C) 40*91f16700Schasinglulu #define PMC_TSC_MULT_0 U(0x2B4) 41*91f16700Schasinglulu #define PMC_STICKY_BIT U(0x2C0) 42*91f16700Schasinglulu #define PMC_SECURE_DISABLE2 U(0x2C4) 43*91f16700Schasinglulu #define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) 44*91f16700Schasinglulu #define PMC_FUSE_CONTROL_0 U(0x450) 45*91f16700Schasinglulu #define PMC_SECURE_DISABLE3 U(0x2D8) 46*91f16700Schasinglulu #define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) 47*91f16700Schasinglulu #define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) 48*91f16700Schasinglulu #define PMC_SECURE_SCRATCH22 U(0x338) 49*91f16700Schasinglulu #define PMC_SECURE_SCRATCH34 U(0x368) 50*91f16700Schasinglulu #define PMC_SECURE_SCRATCH35 U(0x36c) 51*91f16700Schasinglulu #define PMC_SCRATCH56 U(0x600) 52*91f16700Schasinglulu #define PMC_SCRATCH57 U(0x604) 53*91f16700Schasinglulu #define PMC_SCRATCH201 U(0x844) 54*91f16700Schasinglulu 55*91f16700Schasinglulu static inline uint32_t tegra_pmc_read_32(uint32_t off) 56*91f16700Schasinglulu { 57*91f16700Schasinglulu return mmio_read_32(TEGRA_PMC_BASE + off); 58*91f16700Schasinglulu } 59*91f16700Schasinglulu 60*91f16700Schasinglulu static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) 61*91f16700Schasinglulu { 62*91f16700Schasinglulu mmio_write_32(TEGRA_PMC_BASE + off, val); 63*91f16700Schasinglulu } 64*91f16700Schasinglulu 65*91f16700Schasinglulu void tegra_pmc_cpu_on(int32_t cpu); 66*91f16700Schasinglulu void tegra_pmc_cpu_setup(uint64_t reset_addr); 67*91f16700Schasinglulu bool tegra_pmc_is_last_on_cpu(void); 68*91f16700Schasinglulu void tegra_pmc_lock_cpu_vectors(void); 69*91f16700Schasinglulu void tegra_pmc_resume(void); 70*91f16700Schasinglulu __dead2 void tegra_pmc_system_reset(void); 71*91f16700Schasinglulu 72*91f16700Schasinglulu #endif /* PMC_H */ 73