1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef MEMCTRL_V2_H 9*91f16700Schasinglulu #define MEMCTRL_V2_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <tegra_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /******************************************************************************* 16*91f16700Schasinglulu * Memory Controller SMMU Bypass config register 17*91f16700Schasinglulu ******************************************************************************/ 18*91f16700Schasinglulu #define MC_SMMU_BYPASS_CONFIG 0x1820U 19*91f16700Schasinglulu #define MC_SMMU_BYPASS_CTRL_MASK 0x3U 20*91f16700Schasinglulu #define MC_SMMU_BYPASS_CTRL_SHIFT 0U 21*91f16700Schasinglulu #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT) 22*91f16700Schasinglulu #define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT) 23*91f16700Schasinglulu #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT) 24*91f16700Schasinglulu #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT) 25*91f16700Schasinglulu #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31) 26*91f16700Schasinglulu #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 27*91f16700Schasinglulu MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #ifndef __ASSEMBLER__ 30*91f16700Schasinglulu 31*91f16700Schasinglulu #include <assert.h> 32*91f16700Schasinglulu 33*91f16700Schasinglulu typedef struct mc_regs { 34*91f16700Schasinglulu uint32_t reg; 35*91f16700Schasinglulu uint32_t val; 36*91f16700Schasinglulu } mc_regs_t; 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define mc_smmu_bypass_cfg \ 39*91f16700Schasinglulu { \ 40*91f16700Schasinglulu .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ 41*91f16700Schasinglulu .val = 0x00000000U, \ 42*91f16700Schasinglulu } 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define _START_OF_TABLE_ \ 45*91f16700Schasinglulu { \ 46*91f16700Schasinglulu .reg = 0xCAFE05C7U, \ 47*91f16700Schasinglulu .val = 0x00000000U, \ 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define _END_OF_TABLE_ \ 51*91f16700Schasinglulu { \ 52*91f16700Schasinglulu .reg = 0xFFFFFFFFU, \ 53*91f16700Schasinglulu .val = 0xFFFFFFFFU, \ 54*91f16700Schasinglulu } 55*91f16700Schasinglulu 56*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 57*91f16700Schasinglulu 58*91f16700Schasinglulu #ifndef __ASSEMBLER__ 59*91f16700Schasinglulu 60*91f16700Schasinglulu #include <lib/mmio.h> 61*91f16700Schasinglulu 62*91f16700Schasinglulu static inline uint32_t tegra_mc_read_32(uint32_t off) 63*91f16700Schasinglulu { 64*91f16700Schasinglulu return mmio_read_32(TEGRA_MC_BASE + off); 65*91f16700Schasinglulu } 66*91f16700Schasinglulu 67*91f16700Schasinglulu static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu mmio_write_32(TEGRA_MC_BASE + off, val); 70*91f16700Schasinglulu } 71*91f16700Schasinglulu 72*91f16700Schasinglulu #if defined(TEGRA_MC_STREAMID_BASE) 73*91f16700Schasinglulu static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 74*91f16700Schasinglulu { 75*91f16700Schasinglulu return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 76*91f16700Schasinglulu } 77*91f16700Schasinglulu 78*91f16700Schasinglulu static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 79*91f16700Schasinglulu { 80*91f16700Schasinglulu mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 81*91f16700Schasinglulu assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val); 82*91f16700Schasinglulu } 83*91f16700Schasinglulu #endif 84*91f16700Schasinglulu 85*91f16700Schasinglulu void plat_memctrl_setup(void); 86*91f16700Schasinglulu 87*91f16700Schasinglulu void plat_memctrl_restore(void); 88*91f16700Schasinglulu mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void); 89*91f16700Schasinglulu 90*91f16700Schasinglulu /******************************************************************************* 91*91f16700Schasinglulu * Handler to save MC settings before "System Suspend" to TZDRAM 92*91f16700Schasinglulu * 93*91f16700Schasinglulu * Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl 94*91f16700Schasinglulu ******************************************************************************/ 95*91f16700Schasinglulu void tegra_mc_save_context(uint64_t mc_ctx_addr); 96*91f16700Schasinglulu 97*91f16700Schasinglulu /******************************************************************************* 98*91f16700Schasinglulu * Handler to program the scratch registers with TZDRAM settings for the 99*91f16700Schasinglulu * resume firmware. 100*91f16700Schasinglulu * 101*91f16700Schasinglulu * Implemented by SoCs under tegra/soc/txxx 102*91f16700Schasinglulu ******************************************************************************/ 103*91f16700Schasinglulu void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes); 104*91f16700Schasinglulu 105*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 106*91f16700Schasinglulu 107*91f16700Schasinglulu #endif /* MEMCTRL_V2_H */ 108