1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MEMCTRL_V1_H 8*91f16700Schasinglulu #define MEMCTRL_V1_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <tegra_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* SMMU registers */ 15*91f16700Schasinglulu #define MC_SMMU_CONFIG_0 0x10U 16*91f16700Schasinglulu #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U 17*91f16700Schasinglulu #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U 18*91f16700Schasinglulu #define MC_SMMU_TLB_CONFIG_0 0x14U 19*91f16700Schasinglulu #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U 20*91f16700Schasinglulu #define MC_SMMU_PTC_CONFIG_0 0x18U 21*91f16700Schasinglulu #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU 22*91f16700Schasinglulu #define MC_SMMU_TLB_FLUSH_0 0x30U 23*91f16700Schasinglulu #define TLB_FLUSH_VA_MATCH_ALL 0U 24*91f16700Schasinglulu #define TLB_FLUSH_ASID_MATCH_DISABLE 0U 25*91f16700Schasinglulu #define TLB_FLUSH_ASID_MATCH_SHIFT 31U 26*91f16700Schasinglulu #define MC_SMMU_TLB_FLUSH_ALL \ 27*91f16700Schasinglulu (TLB_FLUSH_VA_MATCH_ALL | \ 28*91f16700Schasinglulu (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 29*91f16700Schasinglulu #define MC_SMMU_PTC_FLUSH_0 0x34U 30*91f16700Schasinglulu #define MC_SMMU_PTC_FLUSH_ALL 0U 31*91f16700Schasinglulu #define MC_SMMU_ASID_SECURITY_0 0x38U 32*91f16700Schasinglulu #define MC_SMMU_ASID_SECURITY 0U 33*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U 34*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU 35*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U 36*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U 37*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U 38*91f16700Schasinglulu #define MC_SMMU_TRANSLATION_ENABLE (~0) 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* MC IRAM aperture registers */ 41*91f16700Schasinglulu #define MC_IRAM_BASE_LO 0x65CU 42*91f16700Schasinglulu #define MC_IRAM_TOP_LO 0x660U 43*91f16700Schasinglulu #define MC_IRAM_BASE_TOP_HI 0x980U 44*91f16700Schasinglulu #define MC_IRAM_REG_CTRL 0x964U 45*91f16700Schasinglulu #define MC_DISABLE_IRAM_CFG_WRITES 1U 46*91f16700Schasinglulu 47*91f16700Schasinglulu static inline uint32_t tegra_mc_read_32(uint32_t off) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu return mmio_read_32(TEGRA_MC_BASE + off); 50*91f16700Schasinglulu } 51*91f16700Schasinglulu 52*91f16700Schasinglulu static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu mmio_write_32(TEGRA_MC_BASE + off, val); 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu #endif /* MEMCTRL_V1_H */ 58