1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef MEMCTRL_H 9*91f16700Schasinglulu #define MEMCTRL_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu void tegra_memctrl_setup(void); 12*91f16700Schasinglulu void tegra_memctrl_restore_settings(void); 13*91f16700Schasinglulu void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); 14*91f16700Schasinglulu void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); 15*91f16700Schasinglulu void tegra_memctrl_disable_ahb_redirection(void); 16*91f16700Schasinglulu void tegra_memctrl_clear_pending_interrupts(void); 17*91f16700Schasinglulu 18*91f16700Schasinglulu #endif /* MEMCTRL_H */ 19