1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MCE_H 8*91f16700Schasinglulu #define MCE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <tegra_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /******************************************************************************* 15*91f16700Schasinglulu * MCE commands 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu typedef enum mce_cmd { 18*91f16700Schasinglulu MCE_CMD_ENTER_CSTATE = 0U, 19*91f16700Schasinglulu MCE_CMD_UPDATE_CSTATE_INFO = 1U, 20*91f16700Schasinglulu MCE_CMD_UPDATE_CROSSOVER_TIME = 2U, 21*91f16700Schasinglulu MCE_CMD_READ_CSTATE_STATS = 3U, 22*91f16700Schasinglulu MCE_CMD_WRITE_CSTATE_STATS = 4U, 23*91f16700Schasinglulu MCE_CMD_IS_SC7_ALLOWED = 5U, 24*91f16700Schasinglulu MCE_CMD_ONLINE_CORE = 6U, 25*91f16700Schasinglulu MCE_CMD_CC3_CTRL = 7U, 26*91f16700Schasinglulu MCE_CMD_ECHO_DATA = 8U, 27*91f16700Schasinglulu MCE_CMD_READ_VERSIONS = 9U, 28*91f16700Schasinglulu MCE_CMD_ENUM_FEATURES = 10U, 29*91f16700Schasinglulu MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U, 30*91f16700Schasinglulu MCE_CMD_ENUM_READ_MCA = 12U, 31*91f16700Schasinglulu MCE_CMD_ENUM_WRITE_MCA = 13U, 32*91f16700Schasinglulu MCE_CMD_ROC_FLUSH_CACHE = 14U, 33*91f16700Schasinglulu MCE_CMD_ROC_CLEAN_CACHE = 15U, 34*91f16700Schasinglulu MCE_CMD_ENABLE_LATIC = 16U, 35*91f16700Schasinglulu MCE_CMD_UNCORE_PERFMON_REQ = 17U, 36*91f16700Schasinglulu MCE_CMD_MISC_CCPLEX = 18U, 37*91f16700Schasinglulu MCE_CMD_IS_CCX_ALLOWED = 0xFEU, 38*91f16700Schasinglulu MCE_CMD_MAX = 0xFFU, 39*91f16700Schasinglulu } mce_cmd_t; 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define MCE_CMD_MASK 0xFFU 42*91f16700Schasinglulu 43*91f16700Schasinglulu /******************************************************************************* 44*91f16700Schasinglulu * Timeout value used to powerdown a core 45*91f16700Schasinglulu ******************************************************************************/ 46*91f16700Schasinglulu #define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFFU 47*91f16700Schasinglulu 48*91f16700Schasinglulu /******************************************************************************* 49*91f16700Schasinglulu * Struct to prepare UPDATE_CSTATE_INFO request 50*91f16700Schasinglulu ******************************************************************************/ 51*91f16700Schasinglulu typedef struct mce_cstate_info { 52*91f16700Schasinglulu /* cluster cstate value */ 53*91f16700Schasinglulu uint32_t cluster; 54*91f16700Schasinglulu /* ccplex cstate value */ 55*91f16700Schasinglulu uint32_t ccplex; 56*91f16700Schasinglulu /* system cstate value */ 57*91f16700Schasinglulu uint32_t system; 58*91f16700Schasinglulu /* force system state? */ 59*91f16700Schasinglulu uint8_t system_state_force; 60*91f16700Schasinglulu /* wake mask value */ 61*91f16700Schasinglulu uint32_t wake_mask; 62*91f16700Schasinglulu /* update the wake mask? */ 63*91f16700Schasinglulu uint8_t update_wake_mask; 64*91f16700Schasinglulu } mce_cstate_info_t; 65*91f16700Schasinglulu 66*91f16700Schasinglulu /* public interfaces */ 67*91f16700Schasinglulu int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, 68*91f16700Schasinglulu uint64_t arg2); 69*91f16700Schasinglulu int mce_update_reset_vector(void); 70*91f16700Schasinglulu int mce_update_gsc_videomem(void); 71*91f16700Schasinglulu int mce_update_gsc_tzdram(void); 72*91f16700Schasinglulu __dead2 void mce_enter_ccplex_state(uint32_t state_idx); 73*91f16700Schasinglulu void mce_update_cstate_info(const mce_cstate_info_t *cstate); 74*91f16700Schasinglulu void mce_verify_firmware_version(void); 75*91f16700Schasinglulu 76*91f16700Schasinglulu #endif /* MCE_H */ 77