1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef BPMP_IPC_H 9*91f16700Schasinglulu #define BPMP_IPC_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu #include <stdbool.h> 13*91f16700Schasinglulu #include <stdint.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /** 16*91f16700Schasinglulu * Currently supported reset identifiers 17*91f16700Schasinglulu */ 18*91f16700Schasinglulu #define TEGRA_RESET_ID_XUSB_PADCTL U(114) 19*91f16700Schasinglulu #define TEGRA_RESET_ID_GPCDMA U(70) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /** 22*91f16700Schasinglulu * Function to initialise the IPC with the bpmp 23*91f16700Schasinglulu */ 24*91f16700Schasinglulu int32_t tegra_bpmp_ipc_init(void); 25*91f16700Schasinglulu 26*91f16700Schasinglulu /** 27*91f16700Schasinglulu * Handler to reset a module 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id); 30*91f16700Schasinglulu 31*91f16700Schasinglulu /** 32*91f16700Schasinglulu * Handler to enable clock to a module. Only SE device is 33*91f16700Schasinglulu * supported for now. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu int tegra_bpmp_ipc_enable_clock(uint32_t clk_id); 36*91f16700Schasinglulu 37*91f16700Schasinglulu /** 38*91f16700Schasinglulu * Handler to disable clock to a module. Only SE device is 39*91f16700Schasinglulu * supported for now. 40*91f16700Schasinglulu */ 41*91f16700Schasinglulu int tegra_bpmp_ipc_disable_clock(uint32_t clk_id); 42*91f16700Schasinglulu 43*91f16700Schasinglulu #endif /* BPMP_IPC_H */ 44