xref: /arm-trusted-firmware/plat/nvidia/tegra/drivers/bpmp_ipc/ivc.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2017-2020, NVIDIA Corporation. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef BPMP_IVC_H
8*91f16700Schasinglulu #define BPMP_IVC_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <lib/utils_def.h>
11*91f16700Schasinglulu #include <stdint.h>
12*91f16700Schasinglulu #include <stddef.h>
13*91f16700Schasinglulu 
14*91f16700Schasinglulu #define IVC_ALIGN		U(64)
15*91f16700Schasinglulu #define IVC_CHHDR_TX_FIELDS	U(16)
16*91f16700Schasinglulu #define IVC_CHHDR_RX_FIELDS	U(16)
17*91f16700Schasinglulu 
18*91f16700Schasinglulu struct ivc_channel_header;
19*91f16700Schasinglulu 
20*91f16700Schasinglulu struct ivc {
21*91f16700Schasinglulu 	struct ivc_channel_header *rx_channel;
22*91f16700Schasinglulu 	struct ivc_channel_header *tx_channel;
23*91f16700Schasinglulu 	uint32_t w_pos;
24*91f16700Schasinglulu 	uint32_t r_pos;
25*91f16700Schasinglulu 	void (*notify)(const struct ivc *);
26*91f16700Schasinglulu 	uint32_t nframes;
27*91f16700Schasinglulu 	uint32_t frame_size;
28*91f16700Schasinglulu };
29*91f16700Schasinglulu 
30*91f16700Schasinglulu /* callback handler for notify on receiving a response */
31*91f16700Schasinglulu typedef void (* ivc_notify_function)(const struct ivc *);
32*91f16700Schasinglulu 
33*91f16700Schasinglulu int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
34*91f16700Schasinglulu 		uint32_t nframes, uint32_t frame_size,
35*91f16700Schasinglulu 		ivc_notify_function notify);
36*91f16700Schasinglulu size_t tegra_ivc_total_queue_size(size_t queue_size);
37*91f16700Schasinglulu size_t tegra_ivc_align(size_t size);
38*91f16700Schasinglulu int32_t tegra_ivc_channel_notified(struct ivc *ivc);
39*91f16700Schasinglulu void tegra_ivc_channel_reset(const struct ivc *ivc);
40*91f16700Schasinglulu int32_t tegra_ivc_write_advance(struct ivc *ivc);
41*91f16700Schasinglulu void *tegra_ivc_write_get_next_frame(const struct ivc *ivc);
42*91f16700Schasinglulu int32_t tegra_ivc_write(struct ivc *ivc, const void *buf, size_t size);
43*91f16700Schasinglulu int32_t tegra_ivc_read_advance(struct ivc *ivc);
44*91f16700Schasinglulu void *tegra_ivc_read_get_next_frame(const struct ivc *ivc);
45*91f16700Schasinglulu int32_t tegra_ivc_read(struct ivc *ivc, void *buf, size_t max_read);
46*91f16700Schasinglulu bool tegra_ivc_tx_empty(const struct ivc *ivc);
47*91f16700Schasinglulu bool tegra_ivc_can_write(const struct ivc *ivc);
48*91f16700Schasinglulu bool tegra_ivc_can_read(const struct ivc *ivc);
49*91f16700Schasinglulu 
50*91f16700Schasinglulu #endif /* BPMP_IVC_H */
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