1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/bl_common.h> 10*91f16700Schasinglulu #include <drivers/arm/gicv3.h> 11*91f16700Schasinglulu #include <lib/utils.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat/common/platform.h> 14*91f16700Schasinglulu #include <platform_def.h> 15*91f16700Schasinglulu #include <tegra_private.h> 16*91f16700Schasinglulu #include <tegra_def.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* The GICv3 driver only needs to be initialized in EL3 */ 19*91f16700Schasinglulu static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 20*91f16700Schasinglulu 21*91f16700Schasinglulu static unsigned int plat_tegra_mpidr_to_core_pos(unsigned long mpidr) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu return (unsigned int)plat_core_pos_by_mpidr(mpidr); 24*91f16700Schasinglulu } 25*91f16700Schasinglulu 26*91f16700Schasinglulu /****************************************************************************** 27*91f16700Schasinglulu * Tegra common helper to setup the GICv3 driver data. 28*91f16700Schasinglulu *****************************************************************************/ 29*91f16700Schasinglulu void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 30*91f16700Schasinglulu unsigned int interrupt_props_num) 31*91f16700Schasinglulu { 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * Tegra GIC configuration settings 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu static gicv3_driver_data_t tegra_gic_data; 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* 38*91f16700Schasinglulu * Register Tegra GICv3 driver 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu tegra_gic_data.gicd_base = TEGRA_GICD_BASE; 41*91f16700Schasinglulu tegra_gic_data.gicr_base = TEGRA_GICR_BASE; 42*91f16700Schasinglulu tegra_gic_data.rdistif_num = PLATFORM_CORE_COUNT; 43*91f16700Schasinglulu tegra_gic_data.rdistif_base_addrs = rdistif_base_addrs; 44*91f16700Schasinglulu tegra_gic_data.mpidr_to_core_pos = plat_tegra_mpidr_to_core_pos; 45*91f16700Schasinglulu tegra_gic_data.interrupt_props = interrupt_props; 46*91f16700Schasinglulu tegra_gic_data.interrupt_props_num = interrupt_props_num; 47*91f16700Schasinglulu gicv3_driver_init(&tegra_gic_data); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* initialize the GICD and GICR */ 50*91f16700Schasinglulu tegra_gic_init(); 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu /****************************************************************************** 54*91f16700Schasinglulu * Tegra common helper to initialize the GICv3 only driver. 55*91f16700Schasinglulu *****************************************************************************/ 56*91f16700Schasinglulu void tegra_gic_init(void) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu gicv3_distif_init(); 59*91f16700Schasinglulu gicv3_rdistif_init(plat_my_core_pos()); 60*91f16700Schasinglulu gicv3_cpuif_enable(plat_my_core_pos()); 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu /****************************************************************************** 64*91f16700Schasinglulu * Tegra common helper to disable the GICv3 CPU interface 65*91f16700Schasinglulu *****************************************************************************/ 66*91f16700Schasinglulu void tegra_gic_cpuif_deactivate(void) 67*91f16700Schasinglulu { 68*91f16700Schasinglulu gicv3_cpuif_disable(plat_my_core_pos()); 69*91f16700Schasinglulu } 70*91f16700Schasinglulu 71*91f16700Schasinglulu /****************************************************************************** 72*91f16700Schasinglulu * Tegra common helper to initialize the per cpu distributor interface 73*91f16700Schasinglulu * in GICv3 74*91f16700Schasinglulu *****************************************************************************/ 75*91f16700Schasinglulu void tegra_gic_pcpu_init(void) 76*91f16700Schasinglulu { 77*91f16700Schasinglulu gicv3_rdistif_init(plat_my_core_pos()); 78*91f16700Schasinglulu gicv3_cpuif_enable(plat_my_core_pos()); 79*91f16700Schasinglulu } 80