1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <assert.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <common/bl_common.h> 12*91f16700Schasinglulu #include <drivers/arm/gicv2.h> 13*91f16700Schasinglulu #include <lib/utils.h> 14*91f16700Schasinglulu #include <plat/common/platform.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #include <tegra_private.h> 17*91f16700Schasinglulu #include <tegra_def.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT]; 20*91f16700Schasinglulu 21*91f16700Schasinglulu /****************************************************************************** 22*91f16700Schasinglulu * Tegra common helper to setup the GICv2 driver data. 23*91f16700Schasinglulu *****************************************************************************/ 24*91f16700Schasinglulu void tegra_gic_setup(const interrupt_prop_t *interrupt_props, 25*91f16700Schasinglulu unsigned int interrupt_props_num) 26*91f16700Schasinglulu { 27*91f16700Schasinglulu /* 28*91f16700Schasinglulu * Tegra GIC configuration settings 29*91f16700Schasinglulu */ 30*91f16700Schasinglulu static gicv2_driver_data_t tegra_gic_data; 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * Register Tegra GICv2 driver 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu tegra_gic_data.gicd_base = TEGRA_GICD_BASE; 36*91f16700Schasinglulu tegra_gic_data.gicc_base = TEGRA_GICC_BASE; 37*91f16700Schasinglulu tegra_gic_data.interrupt_props = interrupt_props; 38*91f16700Schasinglulu tegra_gic_data.interrupt_props_num = interrupt_props_num; 39*91f16700Schasinglulu tegra_gic_data.target_masks = tegra_target_masks; 40*91f16700Schasinglulu tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks); 41*91f16700Schasinglulu gicv2_driver_init(&tegra_gic_data); 42*91f16700Schasinglulu } 43*91f16700Schasinglulu 44*91f16700Schasinglulu /****************************************************************************** 45*91f16700Schasinglulu * Tegra common helper to initialize the GICv2 only driver. 46*91f16700Schasinglulu *****************************************************************************/ 47*91f16700Schasinglulu void tegra_gic_init(void) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu gicv2_distif_init(); 50*91f16700Schasinglulu gicv2_pcpu_distif_init(); 51*91f16700Schasinglulu gicv2_set_pe_target_mask(plat_my_core_pos()); 52*91f16700Schasinglulu gicv2_cpuif_enable(); 53*91f16700Schasinglulu } 54*91f16700Schasinglulu 55*91f16700Schasinglulu /****************************************************************************** 56*91f16700Schasinglulu * Tegra common helper to disable the GICv2 CPU interface 57*91f16700Schasinglulu *****************************************************************************/ 58*91f16700Schasinglulu void tegra_gic_cpuif_deactivate(void) 59*91f16700Schasinglulu { 60*91f16700Schasinglulu gicv2_cpuif_disable(); 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu /****************************************************************************** 64*91f16700Schasinglulu * Tegra common helper to initialize the per cpu distributor interface 65*91f16700Schasinglulu * in GICv2 66*91f16700Schasinglulu *****************************************************************************/ 67*91f16700Schasinglulu void tegra_gic_pcpu_init(void) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu gicv2_pcpu_distif_init(); 70*91f16700Schasinglulu gicv2_set_pe_target_mask(plat_my_core_pos()); 71*91f16700Schasinglulu gicv2_cpuif_enable(); 72*91f16700Schasinglulu } 73