xref: /arm-trusted-firmware/plat/nuvoton/common/nuvoton_topology.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * Copyright (C) 2022-2023 Nuvoton Ltd.
5*91f16700Schasinglulu  *
6*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
7*91f16700Schasinglulu  */
8*91f16700Schasinglulu 
9*91f16700Schasinglulu #include <arch.h>
10*91f16700Schasinglulu #include <arch_helpers.h>
11*91f16700Schasinglulu #include <common/debug.h>
12*91f16700Schasinglulu #include <lib/psci/psci.h>
13*91f16700Schasinglulu #include <lib/semihosting.h>
14*91f16700Schasinglulu #include <plat/common/platform.h>
15*91f16700Schasinglulu 
16*91f16700Schasinglulu /*
17*91f16700Schasinglulu  * Since NPCM845 have only powered/non-powered state,
18*91f16700Schasinglulu  * the tree is structure of level 0
19*91f16700Schasinglulu  * (Single cluster == 0) and 4 representing a "leaf" for every CPU
20*91f16700Schasinglulu  */
21*91f16700Schasinglulu const unsigned char npcm845x_power_domain_tree_desc[] = {
22*91f16700Schasinglulu 	PLATFORM_CLUSTER_COUNT,
23*91f16700Schasinglulu 	PLATFORM_MAX_CPU_PER_CLUSTER
24*91f16700Schasinglulu };
25*91f16700Schasinglulu 
26*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void)
27*91f16700Schasinglulu {
28*91f16700Schasinglulu 	/* A single cluster with 4 CPUs */
29*91f16700Schasinglulu 	return npcm845x_power_domain_tree_desc;
30*91f16700Schasinglulu }
31*91f16700Schasinglulu 
32*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr)
33*91f16700Schasinglulu {
34*91f16700Schasinglulu 	unsigned int cluster_id, cpu_id;
35*91f16700Schasinglulu 
36*91f16700Schasinglulu 	mpidr &= MPIDR_AFFINITY_MASK;
37*91f16700Schasinglulu 
38*91f16700Schasinglulu 	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
39*91f16700Schasinglulu 		return -1;
40*91f16700Schasinglulu 	}
41*91f16700Schasinglulu 
42*91f16700Schasinglulu 	cluster_id = (unsigned int)MPIDR_AFFLVL1_VAL(mpidr);
43*91f16700Schasinglulu 	cpu_id = (unsigned int)MPIDR_AFFLVL0_VAL(mpidr);
44*91f16700Schasinglulu 
45*91f16700Schasinglulu 	if (cluster_id > PLATFORM_CLUSTER_COUNT ||
46*91f16700Schasinglulu 		cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) {
47*91f16700Schasinglulu 		return -1;
48*91f16700Schasinglulu 	}
49*91f16700Schasinglulu 
50*91f16700Schasinglulu 	return (int)(cpu_id + (cluster_id * 4));
51*91f16700Schasinglulu }
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