1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <common/runtime_svc.h> 9*91f16700Schasinglulu #include <emi_mpu.h> 10*91f16700Schasinglulu #include <mt_dp.h> 11*91f16700Schasinglulu #include <mt_spm.h> 12*91f16700Schasinglulu #include <mt_spm_vcorefs.h> 13*91f16700Schasinglulu #include <mtk_apusys.h> 14*91f16700Schasinglulu #include <mtk_sip_svc.h> 15*91f16700Schasinglulu #include <plat_dfd.h> 16*91f16700Schasinglulu #include "plat_sip_calls.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid, 19*91f16700Schasinglulu u_register_t x1, 20*91f16700Schasinglulu u_register_t x2, 21*91f16700Schasinglulu u_register_t x3, 22*91f16700Schasinglulu u_register_t x4, 23*91f16700Schasinglulu void *cookie, 24*91f16700Schasinglulu void *handle, 25*91f16700Schasinglulu u_register_t flags) 26*91f16700Schasinglulu { 27*91f16700Schasinglulu int32_t ret; 28*91f16700Schasinglulu uint32_t ret_val; 29*91f16700Schasinglulu 30*91f16700Schasinglulu switch (smc_fid) { 31*91f16700Schasinglulu case MTK_SIP_TEE_MPU_PERM_SET_AARCH64: 32*91f16700Schasinglulu case MTK_SIP_TEE_MPU_PERM_SET_AARCH32: 33*91f16700Schasinglulu ret = emi_mpu_sip_handler(x1, x2, x3); 34*91f16700Schasinglulu SMC_RET2(handle, ret, ret_val); 35*91f16700Schasinglulu break; 36*91f16700Schasinglulu case MTK_SIP_DP_CONTROL_AARCH32: 37*91f16700Schasinglulu case MTK_SIP_DP_CONTROL_AARCH64: 38*91f16700Schasinglulu ret = dp_secure_handler(x1, x2, &ret_val); 39*91f16700Schasinglulu SMC_RET2(handle, ret, ret_val); 40*91f16700Schasinglulu break; 41*91f16700Schasinglulu case MTK_SIP_VCORE_CONTROL_AARCH32: 42*91f16700Schasinglulu case MTK_SIP_VCORE_CONTROL_AARCH64: 43*91f16700Schasinglulu ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); 44*91f16700Schasinglulu SMC_RET2(handle, ret, x4); 45*91f16700Schasinglulu break; 46*91f16700Schasinglulu case MTK_SIP_KERNEL_DFD_AARCH32: 47*91f16700Schasinglulu case MTK_SIP_KERNEL_DFD_AARCH64: 48*91f16700Schasinglulu ret = dfd_smc_dispatcher(x1, x2, x3, x4); 49*91f16700Schasinglulu SMC_RET1(handle, ret); 50*91f16700Schasinglulu break; 51*91f16700Schasinglulu case MTK_SIP_APUSYS_CONTROL_AARCH32: 52*91f16700Schasinglulu case MTK_SIP_APUSYS_CONTROL_AARCH64: 53*91f16700Schasinglulu ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); 54*91f16700Schasinglulu SMC_RET2(handle, ret, ret_val); 55*91f16700Schasinglulu break; 56*91f16700Schasinglulu default: 57*91f16700Schasinglulu ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 58*91f16700Schasinglulu break; 59*91f16700Schasinglulu } 60*91f16700Schasinglulu 61*91f16700Schasinglulu SMC_RET1(handle, SMC_UNK); 62*91f16700Schasinglulu } 63