1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SPM_RESOURCE_REQ_H 8*91f16700Schasinglulu #define MT_SPM_RESOURCE_REQ_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* SPM resource request internal bit */ 11*91f16700Schasinglulu #define MT_SPM_BIT_XO_FPM 0 12*91f16700Schasinglulu #define MT_SPM_BIT_26M 1 13*91f16700Schasinglulu #define MT_SPM_BIT_INFRA 2 14*91f16700Schasinglulu #define MT_SPM_BIT_SYSPLL 3 15*91f16700Schasinglulu #define MT_SPM_BIT_DRAM_S0 4 16*91f16700Schasinglulu #define MT_SPM_BIT_DRAM_S1 5 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* SPM resource request internal bit_mask */ 19*91f16700Schasinglulu #define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM) 20*91f16700Schasinglulu #define MT_SPM_26M BIT(MT_SPM_BIT_26M) 21*91f16700Schasinglulu #define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA) 22*91f16700Schasinglulu #define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL) 23*91f16700Schasinglulu #define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0) 24*91f16700Schasinglulu #define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1) 25*91f16700Schasinglulu #endif /* MT_SPM_RESOURCE_REQ_H */ 26