1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu /**************************************************************** 8*91f16700Schasinglulu * Auto generated by DE, please DO NOT modify this file directly. 9*91f16700Schasinglulu *****************************************************************/ 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifndef MT_SPM_REG 12*91f16700Schasinglulu #define MT_SPM_REG 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include "sleep_def.h" 15*91f16700Schasinglulu #include <platform_def.h> 16*91f16700Schasinglulu #include "pcm_def.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu /************************************** 19*91f16700Schasinglulu * Define and Declare 20*91f16700Schasinglulu **************************************/ 21*91f16700Schasinglulu 22*91f16700Schasinglulu /*******Register_SPM_CFG*************************************************/ 23*91f16700Schasinglulu #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 24*91f16700Schasinglulu #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 25*91f16700Schasinglulu #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 26*91f16700Schasinglulu #define SPM_CLK_CON (SPM_BASE + 0x00C) 27*91f16700Schasinglulu #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 28*91f16700Schasinglulu #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 29*91f16700Schasinglulu #define PCM_CON0 (SPM_BASE + 0x018) 30*91f16700Schasinglulu #define PCM_CON1 (SPM_BASE + 0x01C) 31*91f16700Schasinglulu #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020) 32*91f16700Schasinglulu #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024) 33*91f16700Schasinglulu #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 34*91f16700Schasinglulu #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 35*91f16700Schasinglulu #define PCM_TIMER_VAL (SPM_BASE + 0x030) 36*91f16700Schasinglulu #define PCM_WDT_VAL (SPM_BASE + 0x034) 37*91f16700Schasinglulu #define SPM_SW_RST_CON (SPM_BASE + 0x040) 38*91f16700Schasinglulu #define SPM_SW_RST_CON_SET (SPM_BASE + 0x044) 39*91f16700Schasinglulu #define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048) 40*91f16700Schasinglulu #define VS1_PSR_MASK_B (SPM_BASE + 0x04C) 41*91f16700Schasinglulu #define SPM_ARBITER_EN (SPM_BASE + 0x050) 42*91f16700Schasinglulu #define SCPSYS_CLK_CON (SPM_BASE + 0x054) 43*91f16700Schasinglulu #define SPM_SRAM_RSV_CON (SPM_BASE + 0x058) 44*91f16700Schasinglulu #define SPM_SWINT (SPM_BASE + 0x05C) 45*91f16700Schasinglulu #define SPM_SWINT_SET (SPM_BASE + 0x060) 46*91f16700Schasinglulu #define SPM_SWINT_CLR (SPM_BASE + 0x064) 47*91f16700Schasinglulu #define SPM_SCP_MAILBOX (SPM_BASE + 0x068) 48*91f16700Schasinglulu #define SCP_SPM_MAILBOX (SPM_BASE + 0x06C) 49*91f16700Schasinglulu #define SPM_SCP_IRQ (SPM_BASE + 0x070) 50*91f16700Schasinglulu #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x074) 51*91f16700Schasinglulu #define SPM_IRQ_MASK (SPM_BASE + 0x078) 52*91f16700Schasinglulu #define SPM_SRC_REQ (SPM_BASE + 0x080) 53*91f16700Schasinglulu #define SPM_SRC_MASK (SPM_BASE + 0x084) 54*91f16700Schasinglulu #define SPM_SRC2_MASK (SPM_BASE + 0x088) 55*91f16700Schasinglulu #define SPM_SRC3_MASK (SPM_BASE + 0x090) 56*91f16700Schasinglulu #define SPM_SRC4_MASK (SPM_BASE + 0x094) 57*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MASK2 (SPM_BASE + 0x098) 58*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x09C) 59*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0) 60*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4) 61*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0A8) 62*91f16700Schasinglulu #define SCP_CLK_CON (SPM_BASE + 0x0AC) 63*91f16700Schasinglulu #define PCM_DEBUG_CON (SPM_BASE + 0x0B0) 64*91f16700Schasinglulu #define DDREN_DBC_CON (SPM_BASE + 0x0B4) 65*91f16700Schasinglulu #define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0B8) 66*91f16700Schasinglulu #define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0BC) 67*91f16700Schasinglulu #define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0C0) 68*91f16700Schasinglulu #define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0C4) 69*91f16700Schasinglulu #define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0C8) 70*91f16700Schasinglulu #define SPM_SRAM_CON (SPM_BASE + 0x0CC) 71*91f16700Schasinglulu /*******Register_SPM_STA*************************************************/ 72*91f16700Schasinglulu #define PCM_REG0_DATA (SPM_BASE + 0x100) 73*91f16700Schasinglulu #define PCM_REG2_DATA (SPM_BASE + 0x104) 74*91f16700Schasinglulu #define PCM_REG6_DATA (SPM_BASE + 0x108) 75*91f16700Schasinglulu #define PCM_REG7_DATA (SPM_BASE + 0x10C) 76*91f16700Schasinglulu #define PCM_REG13_DATA (SPM_BASE + 0x110) 77*91f16700Schasinglulu #define SRC_REQ_STA_0 (SPM_BASE + 0x114) 78*91f16700Schasinglulu #define SRC_REQ_STA_1 (SPM_BASE + 0x118) 79*91f16700Schasinglulu #define SRC_REQ_STA_2 (SPM_BASE + 0x120) 80*91f16700Schasinglulu #define SRC_REQ_STA_3 (SPM_BASE + 0x124) 81*91f16700Schasinglulu #define SRC_REQ_STA_4 (SPM_BASE + 0x128) 82*91f16700Schasinglulu #define PCM_TIMER_OUT (SPM_BASE + 0x130) 83*91f16700Schasinglulu #define PCM_WDT_OUT (SPM_BASE + 0x134) 84*91f16700Schasinglulu #define SPM_IRQ_STA (SPM_BASE + 0x138) 85*91f16700Schasinglulu #define MD32PCM_WAKEUP_STA (SPM_BASE + 0x13C) 86*91f16700Schasinglulu #define MD32PCM_EVENT_STA (SPM_BASE + 0x140) 87*91f16700Schasinglulu #define SPM_WAKEUP_STA (SPM_BASE + 0x144) 88*91f16700Schasinglulu #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x148) 89*91f16700Schasinglulu #define SPM_WAKEUP_MISC (SPM_BASE + 0x14C) 90*91f16700Schasinglulu #define MM_DVFS_HALT (SPM_BASE + 0x150) 91*91f16700Schasinglulu #define SUBSYS_IDLE_STA (SPM_BASE + 0x164) 92*91f16700Schasinglulu #define PCM_STA (SPM_BASE + 0x168) 93*91f16700Schasinglulu #define PWR_STATUS (SPM_BASE + 0x16C) 94*91f16700Schasinglulu #define PWR_STATUS_2ND (SPM_BASE + 0x170) 95*91f16700Schasinglulu #define CPU_PWR_STATUS (SPM_BASE + 0x174) 96*91f16700Schasinglulu #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x178) 97*91f16700Schasinglulu #define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C) 98*91f16700Schasinglulu #define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180) 99*91f16700Schasinglulu #define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184) 100*91f16700Schasinglulu #define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188) 101*91f16700Schasinglulu #define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C) 102*91f16700Schasinglulu #define MD32PCM_STA (SPM_BASE + 0x190) 103*91f16700Schasinglulu #define MD32PCM_PC (SPM_BASE + 0x194) 104*91f16700Schasinglulu #define OTHER_PWR_STATUS (SPM_BASE + 0x198) 105*91f16700Schasinglulu #define DVFSRC_EVENT_STA (SPM_BASE + 0x19C) 106*91f16700Schasinglulu #define BUS_PROTECT_RDY (SPM_BASE + 0x1A0) 107*91f16700Schasinglulu #define BUS_PROTECT1_RDY (SPM_BASE + 0x1A4) 108*91f16700Schasinglulu #define BUS_PROTECT2_RDY (SPM_BASE + 0x1A8) 109*91f16700Schasinglulu #define BUS_PROTECT3_RDY (SPM_BASE + 0x1AC) 110*91f16700Schasinglulu #define BUS_PROTECT4_RDY (SPM_BASE + 0x1B0) 111*91f16700Schasinglulu #define BUS_PROTECT5_RDY (SPM_BASE + 0x1B4) 112*91f16700Schasinglulu #define BUS_PROTECT6_RDY (SPM_BASE + 0x1B8) 113*91f16700Schasinglulu #define BUS_PROTECT7_RDY (SPM_BASE + 0x1BC) 114*91f16700Schasinglulu #define BUS_PROTECT8_RDY (SPM_BASE + 0x1C0) 115*91f16700Schasinglulu #define BUS_PROTECT9_RDY (SPM_BASE + 0x1C4) 116*91f16700Schasinglulu #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0) 117*91f16700Schasinglulu #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4) 118*91f16700Schasinglulu #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8) 119*91f16700Schasinglulu #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC) 120*91f16700Schasinglulu #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0) 121*91f16700Schasinglulu #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4) 122*91f16700Schasinglulu #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8) 123*91f16700Schasinglulu #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC) 124*91f16700Schasinglulu #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0) 125*91f16700Schasinglulu #define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4) 126*91f16700Schasinglulu #define SPM_DVFS_STA (SPM_BASE + 0x1F8) 127*91f16700Schasinglulu #define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC) 128*91f16700Schasinglulu /*******Register_CPU_MT*************************************************/ 129*91f16700Schasinglulu #define CPUEB_PWR_CON (SPM_BASE + 0x200) 130*91f16700Schasinglulu #define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x204) 131*91f16700Schasinglulu #define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x208) 132*91f16700Schasinglulu #define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C) 133*91f16700Schasinglulu #define SPM_CPU1_PWR_CON (SPM_BASE + 0x210) 134*91f16700Schasinglulu #define SPM_CPU2_PWR_CON (SPM_BASE + 0x214) 135*91f16700Schasinglulu #define SPM_CPU3_PWR_CON (SPM_BASE + 0x218) 136*91f16700Schasinglulu #define SPM_CPU4_PWR_CON (SPM_BASE + 0x21C) 137*91f16700Schasinglulu #define SPM_CPU5_PWR_CON (SPM_BASE + 0x220) 138*91f16700Schasinglulu #define SPM_CPU6_PWR_CON (SPM_BASE + 0x224) 139*91f16700Schasinglulu #define SPM_CPU7_PWR_CON (SPM_BASE + 0x228) 140*91f16700Schasinglulu #define ARMPLL_CLK_CON (SPM_BASE + 0x22C) 141*91f16700Schasinglulu #define MCUSYS_IDLE_STA (SPM_BASE + 0x230) 142*91f16700Schasinglulu #define GIC_WAKEUP_STA (SPM_BASE + 0x234) 143*91f16700Schasinglulu #define CPU_SPARE_CON (SPM_BASE + 0x238) 144*91f16700Schasinglulu #define CPU_SPARE_CON_SET (SPM_BASE + 0x23C) 145*91f16700Schasinglulu #define CPU_SPARE_CON_CLR (SPM_BASE + 0x240) 146*91f16700Schasinglulu #define ARMPLL_CLK_SEL (SPM_BASE + 0x244) 147*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248) 148*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C) 149*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250) 150*91f16700Schasinglulu #define CPU0_IRQ_MASK (SPM_BASE + 0x260) 151*91f16700Schasinglulu #define CPU_IRQ_MASK_SET (SPM_BASE + 0x264) 152*91f16700Schasinglulu #define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268) 153*91f16700Schasinglulu #define CPU_WFI_EN (SPM_BASE + 0x280) 154*91f16700Schasinglulu #define CPU_WFI_EN_SET (SPM_BASE + 0x284) 155*91f16700Schasinglulu #define CPU_WFI_EN_CLR (SPM_BASE + 0x288) 156*91f16700Schasinglulu #define SYSRAM_CON (SPM_BASE + 0x290) 157*91f16700Schasinglulu #define SYSROM_CON (SPM_BASE + 0x294) 158*91f16700Schasinglulu #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0) 159*91f16700Schasinglulu #define ROOT_CORE_ADDR (SPM_BASE + 0x2A4) 160*91f16700Schasinglulu #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) 161*91f16700Schasinglulu #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4) 162*91f16700Schasinglulu #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8) 163*91f16700Schasinglulu #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC) 164*91f16700Schasinglulu #define SW2SPM_INT (SPM_BASE + 0x2E0) 165*91f16700Schasinglulu #define SW2SPM_INT_SET (SPM_BASE + 0x2E4) 166*91f16700Schasinglulu #define SW2SPM_INT_CLR (SPM_BASE + 0x2E8) 167*91f16700Schasinglulu #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC) 168*91f16700Schasinglulu #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0) 169*91f16700Schasinglulu #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4) 170*91f16700Schasinglulu #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8) 171*91f16700Schasinglulu #define SW2SPM_CFG (SPM_BASE + 0x2FC) 172*91f16700Schasinglulu /*******Register_NONCPU_MT*************************************************/ 173*91f16700Schasinglulu #define MFG0_PWR_CON (SPM_BASE + 0x300) 174*91f16700Schasinglulu #define MFG1_PWR_CON (SPM_BASE + 0x304) 175*91f16700Schasinglulu #define MFG2_PWR_CON (SPM_BASE + 0x308) 176*91f16700Schasinglulu #define MFG3_PWR_CON (SPM_BASE + 0x30C) 177*91f16700Schasinglulu #define MFG4_PWR_CON (SPM_BASE + 0x310) 178*91f16700Schasinglulu #define MFG5_PWR_CON (SPM_BASE + 0x314) 179*91f16700Schasinglulu #define MFG6_PWR_CON (SPM_BASE + 0x318) 180*91f16700Schasinglulu #define IFR_PWR_CON (SPM_BASE + 0x31C) 181*91f16700Schasinglulu #define IFR_SUB_PWR_CON (SPM_BASE + 0x320) 182*91f16700Schasinglulu #define PERI_PWR_CON (SPM_BASE + 0x324) 183*91f16700Schasinglulu #define PEXTP_MAC_TOP_P0_PWR_CON (SPM_BASE + 0x328) 184*91f16700Schasinglulu #define PEXTP_MAC_TOP_P1_PWR_CON (SPM_BASE + 0x32C) 185*91f16700Schasinglulu #define PCIE_PHY_PWR_CON (SPM_BASE + 0x330) 186*91f16700Schasinglulu #define SSUSB_PCIE_PHY_PWR_CON (SPM_BASE + 0x334) 187*91f16700Schasinglulu #define SSUSB_TOP_P1_PWR_CON (SPM_BASE + 0x338) 188*91f16700Schasinglulu #define SSUSB_TOP_P2_PWR_CON (SPM_BASE + 0x33C) 189*91f16700Schasinglulu #define SSUSB_TOP_P3_PWR_CON (SPM_BASE + 0x340) 190*91f16700Schasinglulu #define ETHER_PWR_CON (SPM_BASE + 0x344) 191*91f16700Schasinglulu #define DPY0_PWR_CON (SPM_BASE + 0x348) 192*91f16700Schasinglulu #define DPY1_PWR_CON (SPM_BASE + 0x34C) 193*91f16700Schasinglulu #define DPM0_PWR_CON (SPM_BASE + 0x350) 194*91f16700Schasinglulu #define DPM1_PWR_CON (SPM_BASE + 0x354) 195*91f16700Schasinglulu #define AUDIO_PWR_CON (SPM_BASE + 0x358) 196*91f16700Schasinglulu #define AUDIO_ASRC_PWR_CON (SPM_BASE + 0x35C) 197*91f16700Schasinglulu #define ADSP_PWR_CON (SPM_BASE + 0x360) 198*91f16700Schasinglulu #define VPPSYS0_PWR_CON (SPM_BASE + 0x364) 199*91f16700Schasinglulu #define VPPSYS1_PWR_CON (SPM_BASE + 0x368) 200*91f16700Schasinglulu #define VDOSYS0_PWR_CON (SPM_BASE + 0x36C) 201*91f16700Schasinglulu #define VDOSYS1_PWR_CON (SPM_BASE + 0x370) 202*91f16700Schasinglulu #define WPESYS_PWR_CON (SPM_BASE + 0x374) 203*91f16700Schasinglulu #define DP_TX_PWR_CON (SPM_BASE + 0x378) 204*91f16700Schasinglulu #define EDP_TX_PWR_CON (SPM_BASE + 0x37C) 205*91f16700Schasinglulu #define HDMI_TX_PWR_CON (SPM_BASE + 0x380) 206*91f16700Schasinglulu #define HDMI_RX_PWR_CON (SPM_BASE + 0x384) 207*91f16700Schasinglulu #define VDE0_PWR_CON (SPM_BASE + 0x388) 208*91f16700Schasinglulu #define VDE1_PWR_CON (SPM_BASE + 0x38C) 209*91f16700Schasinglulu #define VDE2_PWR_CON (SPM_BASE + 0x390) 210*91f16700Schasinglulu #define VEN_PWR_CON (SPM_BASE + 0x394) 211*91f16700Schasinglulu #define VEN_CORE1_PWR_CON (SPM_BASE + 0x398) 212*91f16700Schasinglulu #define CAM_PWR_CON (SPM_BASE + 0x39C) 213*91f16700Schasinglulu #define CAM_RAWA_PWR_CON (SPM_BASE + 0x3A0) 214*91f16700Schasinglulu #define CAM_RAWB_PWR_CON (SPM_BASE + 0x3A4) 215*91f16700Schasinglulu #define CAM_RAWC_PWR_CON (SPM_BASE + 0x3A8) 216*91f16700Schasinglulu #define IMG_M_PWR_CON (SPM_BASE + 0x3AC) 217*91f16700Schasinglulu #define IMG_D_PWR_CON (SPM_BASE + 0x3B0) 218*91f16700Schasinglulu #define IPE_PWR_CON (SPM_BASE + 0x3B4) 219*91f16700Schasinglulu #define NNA0_PWR_CON (SPM_BASE + 0x3B8) 220*91f16700Schasinglulu #define NNA1_PWR_CON (SPM_BASE + 0x3BC) 221*91f16700Schasinglulu #define IPNNA_PWR_CON (SPM_BASE + 0x3C0) 222*91f16700Schasinglulu #define CSI_RX_TOP_PWR_CON (SPM_BASE + 0x3C4) 223*91f16700Schasinglulu #define SSPM_SRAM_CON (SPM_BASE + 0x3C4) 224*91f16700Schasinglulu #define SCP_SRAM_CON (SPM_BASE + 0x3D0) 225*91f16700Schasinglulu #define UFS_SRAM_CON (SPM_BASE + 0x3D4) 226*91f16700Schasinglulu #define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x3D8) 227*91f16700Schasinglulu #define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x3DC) 228*91f16700Schasinglulu #define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x3E0) 229*91f16700Schasinglulu #define USB_SRAM_CON (SPM_BASE + 0x3E4) 230*91f16700Schasinglulu #define DUMMY_SRAM_CO (SPM_BASE + 0x3E8) 231*91f16700Schasinglulu #define EXT_BUCK_ISO (SPM_BASE + 0x3EC) 232*91f16700Schasinglulu #define MSDC_SRAM_CON (SPM_BASE + 0x3F0) 233*91f16700Schasinglulu #define DEBUGTOP_SRAM (SPM_BASE + 0x3F4) 234*91f16700Schasinglulu #define DPMAIF_SRAM_C (SPM_BASE + 0x3F8) 235*91f16700Schasinglulu #define GCPU_SRAM_CON (SPM_BASE + 0x3FC) 236*91f16700Schasinglulu /*******Register_DIRC_IF*************************************************/ 237*91f16700Schasinglulu #define SPM_MEM_CK_SEL (SPM_BASE + 0x400) 238*91f16700Schasinglulu #define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404) 239*91f16700Schasinglulu #define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408) 240*91f16700Schasinglulu #define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C) 241*91f16700Schasinglulu #define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410) 242*91f16700Schasinglulu #define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414) 243*91f16700Schasinglulu #define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x418) 244*91f16700Schasinglulu #define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x41C) 245*91f16700Schasinglulu #define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x420) 246*91f16700Schasinglulu #define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x424) 247*91f16700Schasinglulu #define SPM_BUS_PROTECT9_MASK_B (SPM_BASE + 0x428) 248*91f16700Schasinglulu #define SPM_EMI_BW_MODE (SPM_BASE + 0x42C) 249*91f16700Schasinglulu #define SPM2MM_CON (SPM_BASE + 0x434) 250*91f16700Schasinglulu #define SPM2CPUEB_CON (SPM_BASE + 0x438) 251*91f16700Schasinglulu #define AP_MDSRC_REQ (SPM_BASE + 0x43C) 252*91f16700Schasinglulu #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x440) 253*91f16700Schasinglulu #define SPM_PLL_CON (SPM_BASE + 0x444) 254*91f16700Schasinglulu #define RC_SPM_CTRL (SPM_BASE + 0x448) 255*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x44C) 256*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x450) 257*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x454) 258*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x458) 259*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x45C) 260*91f16700Schasinglulu #define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x460) 261*91f16700Schasinglulu #define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x464) 262*91f16700Schasinglulu #define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x468) 263*91f16700Schasinglulu #define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x46C) 264*91f16700Schasinglulu #define RELAY_DVFS_LEVEL (SPM_BASE + 0x470) 265*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x474) 266*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x478) 267*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x47C) 268*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x480) 269*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x484) 270*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x488) 271*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x48C) 272*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x490) 273*91f16700Schasinglulu #define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x494) 274*91f16700Schasinglulu #define SPM_DVFS_LEVEL (SPM_BASE + 0x498) 275*91f16700Schasinglulu #define SPM_CIRQ_CON (SPM_BASE + 0x49C) 276*91f16700Schasinglulu #define SPM_DVFS_MISC (SPM_BASE + 0x4A0) 277*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4A4) 278*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4A8) 279*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4AC) 280*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4B0) 281*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4B4) 282*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4B8) 283*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4BC) 284*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4C0) 285*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4C4) 286*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4C8) 287*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4CC) 288*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4D0) 289*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4D4) 290*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4D8) 291*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4DC) 292*91f16700Schasinglulu #define SPM_CG_CHECK_CON (SPM_BASE + 0x4E0) 293*91f16700Schasinglulu #define SPM_SRC_RDY_STA (SPM_BASE + 0x4E4) 294*91f16700Schasinglulu #define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4E8) 295*91f16700Schasinglulu #define SPM_FORCE_DVFS (SPM_BASE + 0x4EC) 296*91f16700Schasinglulu #define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x4F0) 297*91f16700Schasinglulu #define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x4F4) 298*91f16700Schasinglulu #define DPY_SHU_SRAM_CON (SPM_BASE + 0x4F8) 299*91f16700Schasinglulu #define DPY_SHU2_SRAM_CON (SPM_BASE + 0x4FC) 300*91f16700Schasinglulu /*******The Others*************************************************/ 301*91f16700Schasinglulu #define SRCLKEN_RC_CFG (SPM_BASE + 0x500) 302*91f16700Schasinglulu #define RC_CENTRAL_CFG1 (SPM_BASE + 0x504) 303*91f16700Schasinglulu #define RC_CENTRAL_CFG2 (SPM_BASE + 0x508) 304*91f16700Schasinglulu #define RC_CMD_ARB_CFG (SPM_BASE + 0x50C) 305*91f16700Schasinglulu #define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510) 306*91f16700Schasinglulu #define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514) 307*91f16700Schasinglulu #define RC_DCXO_FPM_CFG (SPM_BASE + 0x518) 308*91f16700Schasinglulu #define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C) 309*91f16700Schasinglulu #define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520) 310*91f16700Schasinglulu #define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524) 311*91f16700Schasinglulu #define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528) 312*91f16700Schasinglulu #define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C) 313*91f16700Schasinglulu #define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530) 314*91f16700Schasinglulu #define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534) 315*91f16700Schasinglulu #define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538) 316*91f16700Schasinglulu #define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C) 317*91f16700Schasinglulu #define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540) 318*91f16700Schasinglulu #define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544) 319*91f16700Schasinglulu #define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548) 320*91f16700Schasinglulu #define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C) 321*91f16700Schasinglulu #define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550) 322*91f16700Schasinglulu #define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554) 323*91f16700Schasinglulu #define RC_CENTRAL_CFG4 (SPM_BASE + 0x558) 324*91f16700Schasinglulu #define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560) 325*91f16700Schasinglulu #define RC_DEBUG_CFG (SPM_BASE + 0x564) 326*91f16700Schasinglulu #define RC_MISC_0 (SPM_BASE + 0x5B4) 327*91f16700Schasinglulu 328*91f16700Schasinglulu #define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC) 329*91f16700Schasinglulu #define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0) 330*91f16700Schasinglulu #define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4) 331*91f16700Schasinglulu #define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8) 332*91f16700Schasinglulu #define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC) 333*91f16700Schasinglulu #define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0) 334*91f16700Schasinglulu #define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4) 335*91f16700Schasinglulu #define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8) 336*91f16700Schasinglulu #define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC) 337*91f16700Schasinglulu #define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0) 338*91f16700Schasinglulu #define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4) 339*91f16700Schasinglulu #define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC) 340*91f16700Schasinglulu #define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0) 341*91f16700Schasinglulu #define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4) 342*91f16700Schasinglulu #define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8) 343*91f16700Schasinglulu #define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC) 344*91f16700Schasinglulu /*******Register_RSV*************************************************/ 345*91f16700Schasinglulu #define SPM_SW_FLAG_0 (SPM_BASE + 0x600) 346*91f16700Schasinglulu #define SPM_SW_DEBUG_0 (SPM_BASE + 0x604) 347*91f16700Schasinglulu #define SPM_SW_FLAG_1 (SPM_BASE + 0x608) 348*91f16700Schasinglulu #define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C) 349*91f16700Schasinglulu #define SPM_SW_RSV_0 (SPM_BASE + 0x610) 350*91f16700Schasinglulu #define SPM_SW_RSV_1 (SPM_BASE + 0x614) 351*91f16700Schasinglulu #define SPM_SW_RSV_2 (SPM_BASE + 0x618) 352*91f16700Schasinglulu #define SPM_SW_RSV_3 (SPM_BASE + 0x61C) 353*91f16700Schasinglulu #define SPM_SW_RSV_4 (SPM_BASE + 0x620) 354*91f16700Schasinglulu #define SPM_SW_RSV_5 (SPM_BASE + 0x624) 355*91f16700Schasinglulu #define SPM_SW_RSV_6 (SPM_BASE + 0x628) 356*91f16700Schasinglulu #define SPM_SW_RSV_7 (SPM_BASE + 0x62C) 357*91f16700Schasinglulu #define SPM_SW_RSV_8 (SPM_BASE + 0x630) 358*91f16700Schasinglulu #define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634) 359*91f16700Schasinglulu #define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638) 360*91f16700Schasinglulu #define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C) 361*91f16700Schasinglulu #define SPM_BK_PCM_TIMER (SPM_BASE + 0x640) 362*91f16700Schasinglulu #define ULPOSC_CON (SPM_BASE + 0x644) 363*91f16700Schasinglulu #define SPM_RSV_CON_0 (SPM_BASE + 0x650) 364*91f16700Schasinglulu #define SPM_RSV_CON_1 (SPM_BASE + 0x654) 365*91f16700Schasinglulu #define SPM_RSV_STA_0 (SPM_BASE + 0x658) 366*91f16700Schasinglulu #define SPM_RSV_STA_1 (SPM_BASE + 0x65C) 367*91f16700Schasinglulu #define SPM_SPARE_CON (SPM_BASE + 0x660) 368*91f16700Schasinglulu #define SPM_SPARE_CON_SET (SPM_BASE + 0x664) 369*91f16700Schasinglulu #define SPM_SPARE_CON_CLR (SPM_BASE + 0x668) 370*91f16700Schasinglulu #define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C) 371*91f16700Schasinglulu #define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670) 372*91f16700Schasinglulu #define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674) 373*91f16700Schasinglulu #define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678) 374*91f16700Schasinglulu #define SCP_VCORE_LEVEL (SPM_BASE + 0x67C) 375*91f16700Schasinglulu #define SC_MM_CK_SEL_CON (SPM_BASE + 0x680) 376*91f16700Schasinglulu #define SPARE_ACK_MASK (SPM_BASE + 0x684) 377*91f16700Schasinglulu #define SPM_DV_CON_0 (SPM_BASE + 0x68C) 378*91f16700Schasinglulu #define SPM_DV_CON_1 (SPM_BASE + 0x690) 379*91f16700Schasinglulu #define SPM_DV_STA (SPM_BASE + 0x694) 380*91f16700Schasinglulu #define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698) 381*91f16700Schasinglulu #define SPM_SEMA_M0 (SPM_BASE + 0x69C) 382*91f16700Schasinglulu #define SPM_SEMA_M1 (SPM_BASE + 0x6A0) 383*91f16700Schasinglulu #define SPM_SEMA_M2 (SPM_BASE + 0x6A4) 384*91f16700Schasinglulu #define SPM_SEMA_M3 (SPM_BASE + 0x6A8) 385*91f16700Schasinglulu #define SPM_SEMA_M4 (SPM_BASE + 0x6AC) 386*91f16700Schasinglulu #define SPM_SEMA_M5 (SPM_BASE + 0x6B0) 387*91f16700Schasinglulu #define SPM_SEMA_M6 (SPM_BASE + 0x6B4) 388*91f16700Schasinglulu #define SPM_SEMA_M7 (SPM_BASE + 0x6B8) 389*91f16700Schasinglulu #define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC) 390*91f16700Schasinglulu #define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0) 391*91f16700Schasinglulu #define SPM_ADSP_IRQ (SPM_BASE + 0x6C4) 392*91f16700Schasinglulu #define SPM_MD32_IRQ (SPM_BASE + 0x6C8) 393*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC) 394*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0) 395*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4) 396*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8) 397*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC) 398*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0) 399*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4) 400*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8) 401*91f16700Schasinglulu #define UFS_PSRI_SW (SPM_BASE + 0x6EC) 402*91f16700Schasinglulu #define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0) 403*91f16700Schasinglulu #define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4) 404*91f16700Schasinglulu #define SPM_AP_SEMA (SPM_BASE + 0x6F8) 405*91f16700Schasinglulu #define SPM_SPM_SEMA (SPM_BASE + 0x6FC) 406*91f16700Schasinglulu /*******Register_DVFS_TAB*************************************************/ 407*91f16700Schasinglulu #define SPM_DVFS_CON (SPM_BASE + 0x700) 408*91f16700Schasinglulu #define SPM_DVFS_CON_STA (SPM_BASE + 0x704) 409*91f16700Schasinglulu #define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708) 410*91f16700Schasinglulu #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 411*91f16700Schasinglulu #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 412*91f16700Schasinglulu #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 413*91f16700Schasinglulu #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 414*91f16700Schasinglulu #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 415*91f16700Schasinglulu #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 416*91f16700Schasinglulu #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 417*91f16700Schasinglulu #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 418*91f16700Schasinglulu #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 419*91f16700Schasinglulu #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 420*91f16700Schasinglulu #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 421*91f16700Schasinglulu #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 422*91f16700Schasinglulu #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 423*91f16700Schasinglulu #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 424*91f16700Schasinglulu #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 425*91f16700Schasinglulu #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 426*91f16700Schasinglulu #define SPM_DVFS_CMD16 (SPM_BASE + 0x750) 427*91f16700Schasinglulu #define SPM_DVFS_CMD17 (SPM_BASE + 0x754) 428*91f16700Schasinglulu #define SPM_DVFS_CMD18 (SPM_BASE + 0x758) 429*91f16700Schasinglulu #define SPM_DVFS_CMD19 (SPM_BASE + 0x75C) 430*91f16700Schasinglulu #define SPM_DVFS_CMD20 (SPM_BASE + 0x760) 431*91f16700Schasinglulu #define SPM_DVFS_CMD21 (SPM_BASE + 0x764) 432*91f16700Schasinglulu #define SPM_DVFS_CMD22 (SPM_BASE + 0x768) 433*91f16700Schasinglulu #define SPM_DVFS_CMD23 (SPM_BASE + 0x76C) 434*91f16700Schasinglulu #define SYS_TIMER_VALUE_L (SPM_BASE + 0x770) 435*91f16700Schasinglulu #define SYS_TIMER_VALUE_H (SPM_BASE + 0x774) 436*91f16700Schasinglulu #define SYS_TIMER_START_L (SPM_BASE + 0x778) 437*91f16700Schasinglulu #define SYS_TIMER_START_H (SPM_BASE + 0x77C) 438*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780) 439*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784) 440*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788) 441*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C) 442*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790) 443*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794) 444*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798) 445*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C) 446*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0) 447*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4) 448*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8) 449*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC) 450*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0) 451*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4) 452*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8) 453*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC) 454*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0) 455*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4) 456*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8) 457*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC) 458*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0) 459*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4) 460*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8) 461*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC) 462*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0) 463*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4) 464*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8) 465*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC) 466*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0) 467*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4) 468*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8) 469*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC) 470*91f16700Schasinglulu /*******Register_LAT_STA*************************************************/ 471*91f16700Schasinglulu #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 472*91f16700Schasinglulu #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 473*91f16700Schasinglulu #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 474*91f16700Schasinglulu #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 475*91f16700Schasinglulu #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 476*91f16700Schasinglulu #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 477*91f16700Schasinglulu #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 478*91f16700Schasinglulu #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 479*91f16700Schasinglulu #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 480*91f16700Schasinglulu #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 481*91f16700Schasinglulu #define PCM_WDT_LATCH_10 (SPM_BASE + 0x828) 482*91f16700Schasinglulu #define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C) 483*91f16700Schasinglulu #define PCM_WDT_LATCH_12 (SPM_BASE + 0x830) 484*91f16700Schasinglulu #define PCM_WDT_LATCH_13 (SPM_BASE + 0x834) 485*91f16700Schasinglulu #define PCM_WDT_LATCH_14 (SPM_BASE + 0x838) 486*91f16700Schasinglulu #define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C) 487*91f16700Schasinglulu #define PCM_WDT_LATCH_16 (SPM_BASE + 0x840) 488*91f16700Schasinglulu #define PCM_WDT_LATCH_17 (SPM_BASE + 0x844) 489*91f16700Schasinglulu #define PCM_WDT_LATCH_18 (SPM_BASE + 0x848) 490*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C) 491*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850) 492*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854) 493*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870) 494*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874) 495*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878) 496*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0) 497*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4) 498*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8) 499*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC) 500*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0) 501*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4) 502*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8) 503*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4) 504*91f16700Schasinglulu /*******Register_SPM_ACK_CHK*************************************************/ 505*91f16700Schasinglulu #define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900) 506*91f16700Schasinglulu #define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904) 507*91f16700Schasinglulu #define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908) 508*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C) 509*91f16700Schasinglulu #define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910) 510*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914) 511*91f16700Schasinglulu #define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920) 512*91f16700Schasinglulu #define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924) 513*91f16700Schasinglulu #define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928) 514*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C) 515*91f16700Schasinglulu #define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930) 516*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934) 517*91f16700Schasinglulu #define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940) 518*91f16700Schasinglulu #define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944) 519*91f16700Schasinglulu #define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948) 520*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C) 521*91f16700Schasinglulu #define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950) 522*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954) 523*91f16700Schasinglulu #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) 524*91f16700Schasinglulu #define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964) 525*91f16700Schasinglulu #define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968) 526*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C) 527*91f16700Schasinglulu #define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970) 528*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974) 529*91f16700Schasinglulu #define SPM_COUNTER_0 (SPM_BASE + 0x978) 530*91f16700Schasinglulu #define SPM_COUNTER_1 (SPM_BASE + 0x97C) 531*91f16700Schasinglulu #define SPM_COUNTER_2 (SPM_BASE + 0x980) 532*91f16700Schasinglulu #define SYS_TIMER_CON (SPM_BASE + 0x98C) 533*91f16700Schasinglulu #define SPM_TWAM_CON (SPM_BASE + 0x990) 534*91f16700Schasinglulu #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x994) 535*91f16700Schasinglulu #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x998) 536*91f16700Schasinglulu #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x99C) 537*91f16700Schasinglulu /*******The OTHERS*************************************************/ 538*91f16700Schasinglulu #define RC_FSM_STA_0 (SPM_BASE + 0xE00) 539*91f16700Schasinglulu #define RC_CMD_STA_0 (SPM_BASE + 0xE04) 540*91f16700Schasinglulu #define RC_CMD_STA_1 (SPM_BASE + 0xE08) 541*91f16700Schasinglulu #define RC_SPI_STA_0 (SPM_BASE + 0xE0C) 542*91f16700Schasinglulu #define RC_PI_PO_STA_0 (SPM_BASE + 0xE10) 543*91f16700Schasinglulu #define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14) 544*91f16700Schasinglulu #define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C) 545*91f16700Schasinglulu #define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20) 546*91f16700Schasinglulu #define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24) 547*91f16700Schasinglulu #define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28) 548*91f16700Schasinglulu #define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C) 549*91f16700Schasinglulu #define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30) 550*91f16700Schasinglulu #define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34) 551*91f16700Schasinglulu #define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38) 552*91f16700Schasinglulu #define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C) 553*91f16700Schasinglulu #define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40) 554*91f16700Schasinglulu #define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44) 555*91f16700Schasinglulu #define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48) 556*91f16700Schasinglulu #define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C) 557*91f16700Schasinglulu #define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50) 558*91f16700Schasinglulu #define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54) 559*91f16700Schasinglulu #define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C) 560*91f16700Schasinglulu #define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60) 561*91f16700Schasinglulu #define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64) 562*91f16700Schasinglulu #define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C) 563*91f16700Schasinglulu #define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70) 564*91f16700Schasinglulu #define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74) 565*91f16700Schasinglulu #define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78) 566*91f16700Schasinglulu #define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C) 567*91f16700Schasinglulu #define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80) 568*91f16700Schasinglulu #define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84) 569*91f16700Schasinglulu #define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88) 570*91f16700Schasinglulu #define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C) 571*91f16700Schasinglulu #define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90) 572*91f16700Schasinglulu #define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94) 573*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98) 574*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C) 575*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0) 576*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4) 577*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8) 578*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC) 579*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0) 580*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4) 581*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8) 582*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC) 583*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0) 584*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4) 585*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8) 586*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC) 587*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0) 588*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4) 589*91f16700Schasinglulu #define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8) 590*91f16700Schasinglulu #define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC) 591*91f16700Schasinglulu #define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0) 592*91f16700Schasinglulu #define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4) 593*91f16700Schasinglulu #define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8) 594*91f16700Schasinglulu #define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC) 595*91f16700Schasinglulu /*******Register_PMSR*************************************************/ 596*91f16700Schasinglulu #define PMSR_LAST_DAT (SPM_BASE + 0xF00) 597*91f16700Schasinglulu #define PMSR_LAST_CNT (SPM_BASE + 0xF04) 598*91f16700Schasinglulu #define PMSR_LAST_ACK (SPM_BASE + 0xF08) 599*91f16700Schasinglulu #define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10) 600*91f16700Schasinglulu #define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14) 601*91f16700Schasinglulu #define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18) 602*91f16700Schasinglulu #define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C) 603*91f16700Schasinglulu #define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20) 604*91f16700Schasinglulu #define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24) 605*91f16700Schasinglulu #define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28) 606*91f16700Schasinglulu #define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C) 607*91f16700Schasinglulu #define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30) 608*91f16700Schasinglulu #define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34) 609*91f16700Schasinglulu #define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C) 610*91f16700Schasinglulu #define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40) 611*91f16700Schasinglulu #define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8) 612*91f16700Schasinglulu #define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC) 613*91f16700Schasinglulu #define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0) 614*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4) 615*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8) 616*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC) 617*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0) 618*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4) 619*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8) 620*91f16700Schasinglulu #define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC) 621*91f16700Schasinglulu #define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0) 622*91f16700Schasinglulu #define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4) 623*91f16700Schasinglulu #define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8) 624*91f16700Schasinglulu #define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC) 625*91f16700Schasinglulu #define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0) 626*91f16700Schasinglulu #define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4) 627*91f16700Schasinglulu /*******Register End*************************************************/ 628*91f16700Schasinglulu 629*91f16700Schasinglulu /* POWERON_CONFIG_EN (0x10006000+0x000) */ 630*91f16700Schasinglulu #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 631*91f16700Schasinglulu #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 632*91f16700Schasinglulu /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ 633*91f16700Schasinglulu #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 634*91f16700Schasinglulu /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ 635*91f16700Schasinglulu #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 636*91f16700Schasinglulu /* SPM_CLK_CON (0x10006000+0x00C) */ 637*91f16700Schasinglulu #define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */ 638*91f16700Schasinglulu #define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */ 639*91f16700Schasinglulu #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 640*91f16700Schasinglulu #define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 641*91f16700Schasinglulu #define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 642*91f16700Schasinglulu #define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */ 643*91f16700Schasinglulu #define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */ 644*91f16700Schasinglulu #define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 645*91f16700Schasinglulu #define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 646*91f16700Schasinglulu #define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */ 647*91f16700Schasinglulu #define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */ 648*91f16700Schasinglulu #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 649*91f16700Schasinglulu #define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */ 650*91f16700Schasinglulu #define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */ 651*91f16700Schasinglulu /* SPM_CLK_SETTLE (0x10006000+0x010) */ 652*91f16700Schasinglulu #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 653*91f16700Schasinglulu /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ 654*91f16700Schasinglulu #define REG_WFI_OP_LSB (1U << 0) /* 1b */ 655*91f16700Schasinglulu #define REG_WFI_TYPE_LSB (1U << 1) /* 1b */ 656*91f16700Schasinglulu #define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 657*91f16700Schasinglulu #define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */ 658*91f16700Schasinglulu #define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 659*91f16700Schasinglulu #define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 660*91f16700Schasinglulu #define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 661*91f16700Schasinglulu #define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 662*91f16700Schasinglulu /* PCM_CON0 (0x10006000+0x018) */ 663*91f16700Schasinglulu #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 664*91f16700Schasinglulu #define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 665*91f16700Schasinglulu #define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */ 666*91f16700Schasinglulu #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 667*91f16700Schasinglulu #define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */ 668*91f16700Schasinglulu /* PCM_CON1 (0x10006000+0x01C) */ 669*91f16700Schasinglulu #define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ 670*91f16700Schasinglulu #define RG_IM_SLEEP_LSB (1U << 1) /* 1b */ 671*91f16700Schasinglulu #define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */ 672*91f16700Schasinglulu #define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ 673*91f16700Schasinglulu #define RG_IM_PDN_LSB (1U << 4) /* 1b */ 674*91f16700Schasinglulu #define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 675*91f16700Schasinglulu #define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ 676*91f16700Schasinglulu #define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 677*91f16700Schasinglulu #define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */ 678*91f16700Schasinglulu #define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ 679*91f16700Schasinglulu #define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 680*91f16700Schasinglulu #define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 681*91f16700Schasinglulu #define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 682*91f16700Schasinglulu #define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 683*91f16700Schasinglulu #define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 684*91f16700Schasinglulu #define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */ 685*91f16700Schasinglulu #define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */ 686*91f16700Schasinglulu /* SPM_POWER_ON_VAL2 (0x10006000+0x020) */ 687*91f16700Schasinglulu #define POWER_ON_VAL2_LSB (1U << 0) /* 32b */ 688*91f16700Schasinglulu /* SPM_POWER_ON_VAL3 (0x10006000+0x024) */ 689*91f16700Schasinglulu #define POWER_ON_VAL3_LSB (1U << 0) /* 32b */ 690*91f16700Schasinglulu /* PCM_REG_DATA_INI (0x10006000+0x028) */ 691*91f16700Schasinglulu #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 692*91f16700Schasinglulu /* PCM_PWR_IO_EN (0x10006000+0x02C) */ 693*91f16700Schasinglulu #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 694*91f16700Schasinglulu #define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 695*91f16700Schasinglulu /* PCM_TIMER_VAL (0x10006000+0x030) */ 696*91f16700Schasinglulu #define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 697*91f16700Schasinglulu /* PCM_WDT_VAL (0x10006000+0x034) */ 698*91f16700Schasinglulu #define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 699*91f16700Schasinglulu /* SPM_SW_RST_CON (0x10006000+0x040) */ 700*91f16700Schasinglulu #define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */ 701*91f16700Schasinglulu #define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */ 702*91f16700Schasinglulu /* SPM_SW_RST_CON_SET (0x10006000+0x044) */ 703*91f16700Schasinglulu #define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */ 704*91f16700Schasinglulu #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */ 705*91f16700Schasinglulu /* SPM_SW_RST_CON_CLR (0x10006000+0x048) */ 706*91f16700Schasinglulu #define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */ 707*91f16700Schasinglulu #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */ 708*91f16700Schasinglulu /* VS1_PSR_MASK_B (0x10006000+0x04C) */ 709*91f16700Schasinglulu #define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 710*91f16700Schasinglulu #define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 711*91f16700Schasinglulu /* VS2_PSR_MASK_B (0x10006000+0x050) */ 712*91f16700Schasinglulu #define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */ 713*91f16700Schasinglulu #define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */ 714*91f16700Schasinglulu #define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */ 715*91f16700Schasinglulu /* MD32_CLK_CON (0x10006000+0x084) */ 716*91f16700Schasinglulu #define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */ 717*91f16700Schasinglulu #define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */ 718*91f16700Schasinglulu /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ 719*91f16700Schasinglulu #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 720*91f16700Schasinglulu /* SPM_SWINT (0x10006000+0x08C) */ 721*91f16700Schasinglulu #define SPM_SWINT_LSB (1U << 0) /* 32b */ 722*91f16700Schasinglulu /* SPM_SWINT_SET (0x10006000+0x090) */ 723*91f16700Schasinglulu #define SPM_SWINT_SET_LSB (1U << 0) /* 32b */ 724*91f16700Schasinglulu /* SPM_SWINT_CLR (0x10006000+0x094) */ 725*91f16700Schasinglulu #define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */ 726*91f16700Schasinglulu /* SPM_SCP_MAILBOX (0x10006000+0x098) */ 727*91f16700Schasinglulu #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 728*91f16700Schasinglulu /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ 729*91f16700Schasinglulu #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 730*91f16700Schasinglulu /* SPM_TWAM_CON (0x10006000+0x0A0) */ 731*91f16700Schasinglulu #define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */ 732*91f16700Schasinglulu #define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */ 733*91f16700Schasinglulu #define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */ 734*91f16700Schasinglulu #define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */ 735*91f16700Schasinglulu #define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */ 736*91f16700Schasinglulu #define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */ 737*91f16700Schasinglulu #define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */ 738*91f16700Schasinglulu #define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */ 739*91f16700Schasinglulu /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ 740*91f16700Schasinglulu #define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 741*91f16700Schasinglulu /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ 742*91f16700Schasinglulu #define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */ 743*91f16700Schasinglulu #define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */ 744*91f16700Schasinglulu #define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */ 745*91f16700Schasinglulu #define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */ 746*91f16700Schasinglulu /* SPM_SCP_IRQ (0x10006000+0x0AC) */ 747*91f16700Schasinglulu #define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */ 748*91f16700Schasinglulu #define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 749*91f16700Schasinglulu /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ 750*91f16700Schasinglulu #define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */ 751*91f16700Schasinglulu /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 752*91f16700Schasinglulu #define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */ 753*91f16700Schasinglulu /* DDR_EN_DBC (0x10006000+0x0B4) */ 754*91f16700Schasinglulu #define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */ 755*91f16700Schasinglulu /* SPM_SRC_REQ (0x10006000+0x0B8) */ 756*91f16700Schasinglulu #define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 757*91f16700Schasinglulu #define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 758*91f16700Schasinglulu #define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 759*91f16700Schasinglulu #define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 760*91f16700Schasinglulu #define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */ 761*91f16700Schasinglulu #define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */ 762*91f16700Schasinglulu #define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */ 763*91f16700Schasinglulu #define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */ 764*91f16700Schasinglulu #define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */ 765*91f16700Schasinglulu #define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */ 766*91f16700Schasinglulu /* SPM_SRC_MASK (0x10006000+0x0BC) */ 767*91f16700Schasinglulu #define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */ 768*91f16700Schasinglulu #define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */ 769*91f16700Schasinglulu #define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */ 770*91f16700Schasinglulu #define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */ 771*91f16700Schasinglulu #define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */ 772*91f16700Schasinglulu #define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */ 773*91f16700Schasinglulu #define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */ 774*91f16700Schasinglulu #define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */ 775*91f16700Schasinglulu #define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */ 776*91f16700Schasinglulu #define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */ 777*91f16700Schasinglulu #define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */ 778*91f16700Schasinglulu #define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */ 779*91f16700Schasinglulu #define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 780*91f16700Schasinglulu #define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */ 781*91f16700Schasinglulu #define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */ 782*91f16700Schasinglulu #define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 783*91f16700Schasinglulu #define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */ 784*91f16700Schasinglulu #define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */ 785*91f16700Schasinglulu #define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */ 786*91f16700Schasinglulu #define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */ 787*91f16700Schasinglulu #define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */ 788*91f16700Schasinglulu #define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */ 789*91f16700Schasinglulu #define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ 790*91f16700Schasinglulu #define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 791*91f16700Schasinglulu #define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 792*91f16700Schasinglulu #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 793*91f16700Schasinglulu #define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 794*91f16700Schasinglulu #define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 795*91f16700Schasinglulu #define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 796*91f16700Schasinglulu #define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 797*91f16700Schasinglulu #define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 798*91f16700Schasinglulu #define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 799*91f16700Schasinglulu /* SPM_SRC2_MASK (0x10006000+0x0C0) */ 800*91f16700Schasinglulu #define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */ 801*91f16700Schasinglulu #define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */ 802*91f16700Schasinglulu #define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */ 803*91f16700Schasinglulu #define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */ 804*91f16700Schasinglulu #define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */ 805*91f16700Schasinglulu #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */ 806*91f16700Schasinglulu #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */ 807*91f16700Schasinglulu #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */ 808*91f16700Schasinglulu #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */ 809*91f16700Schasinglulu #define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */ 810*91f16700Schasinglulu #define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */ 811*91f16700Schasinglulu #define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 812*91f16700Schasinglulu #define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */ 813*91f16700Schasinglulu #define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */ 814*91f16700Schasinglulu #define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */ 815*91f16700Schasinglulu #define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */ 816*91f16700Schasinglulu #define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */ 817*91f16700Schasinglulu #define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */ 818*91f16700Schasinglulu #define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */ 819*91f16700Schasinglulu #define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */ 820*91f16700Schasinglulu #define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */ 821*91f16700Schasinglulu #define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 822*91f16700Schasinglulu #define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */ 823*91f16700Schasinglulu #define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */ 824*91f16700Schasinglulu #define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */ 825*91f16700Schasinglulu #define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 826*91f16700Schasinglulu #define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */ 827*91f16700Schasinglulu #define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */ 828*91f16700Schasinglulu #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */ 829*91f16700Schasinglulu #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 830*91f16700Schasinglulu #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 831*91f16700Schasinglulu #define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 832*91f16700Schasinglulu /* SPM_SRC3_MASK (0x10006000+0x0C4) */ 833*91f16700Schasinglulu #define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */ 834*91f16700Schasinglulu #define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */ 835*91f16700Schasinglulu #define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */ 836*91f16700Schasinglulu #define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */ 837*91f16700Schasinglulu #define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */ 838*91f16700Schasinglulu #define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */ 839*91f16700Schasinglulu #define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */ 840*91f16700Schasinglulu #define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */ 841*91f16700Schasinglulu #define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */ 842*91f16700Schasinglulu #define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */ 843*91f16700Schasinglulu #define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */ 844*91f16700Schasinglulu #define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */ 845*91f16700Schasinglulu #define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */ 846*91f16700Schasinglulu #define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */ 847*91f16700Schasinglulu #define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 848*91f16700Schasinglulu #define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */ 849*91f16700Schasinglulu #define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */ 850*91f16700Schasinglulu #define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 851*91f16700Schasinglulu #define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */ 852*91f16700Schasinglulu #define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */ 853*91f16700Schasinglulu #define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 854*91f16700Schasinglulu #define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 855*91f16700Schasinglulu #define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */ 856*91f16700Schasinglulu #define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */ 857*91f16700Schasinglulu #define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */ 858*91f16700Schasinglulu #define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */ 859*91f16700Schasinglulu #define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */ 860*91f16700Schasinglulu #define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */ 861*91f16700Schasinglulu #define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */ 862*91f16700Schasinglulu /* SPM_SRC4_MASK (0x10006000+0x0C8) */ 863*91f16700Schasinglulu #define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */ 864*91f16700Schasinglulu #define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */ 865*91f16700Schasinglulu #define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */ 866*91f16700Schasinglulu #define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */ 867*91f16700Schasinglulu #define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */ 868*91f16700Schasinglulu #define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */ 869*91f16700Schasinglulu #define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */ 870*91f16700Schasinglulu #define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */ 871*91f16700Schasinglulu #define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */ 872*91f16700Schasinglulu #define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */ 873*91f16700Schasinglulu #define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */ 874*91f16700Schasinglulu #define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */ 875*91f16700Schasinglulu #define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */ 876*91f16700Schasinglulu /* SPM_SRC5_MASK (0x10006000+0x0CC) */ 877*91f16700Schasinglulu #define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */ 878*91f16700Schasinglulu #define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */ 879*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ 880*91f16700Schasinglulu #define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 881*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */ 882*91f16700Schasinglulu #define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 883*91f16700Schasinglulu /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */ 884*91f16700Schasinglulu #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 885*91f16700Schasinglulu /* SCP_CLK_CON (0x10006000+0x0DC) */ 886*91f16700Schasinglulu #define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 887*91f16700Schasinglulu #define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */ 888*91f16700Schasinglulu #define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */ 889*91f16700Schasinglulu #define SCP_SLP_REQ_LSB (1U << 3) /* 1b */ 890*91f16700Schasinglulu #define SCP_SLP_ACK_LSB (1U << 4) /* 1b */ 891*91f16700Schasinglulu /* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */ 892*91f16700Schasinglulu #define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */ 893*91f16700Schasinglulu #define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */ 894*91f16700Schasinglulu #define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */ 895*91f16700Schasinglulu #define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */ 896*91f16700Schasinglulu #define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */ 897*91f16700Schasinglulu #define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */ 898*91f16700Schasinglulu #define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */ 899*91f16700Schasinglulu #define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */ 900*91f16700Schasinglulu #define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */ 901*91f16700Schasinglulu #define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */ 902*91f16700Schasinglulu #define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 903*91f16700Schasinglulu #define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 904*91f16700Schasinglulu #define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 905*91f16700Schasinglulu #define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 906*91f16700Schasinglulu #define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 907*91f16700Schasinglulu #define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 908*91f16700Schasinglulu #define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 909*91f16700Schasinglulu #define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 910*91f16700Schasinglulu #define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 911*91f16700Schasinglulu #define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 912*91f16700Schasinglulu #define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 913*91f16700Schasinglulu #define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 914*91f16700Schasinglulu #define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 915*91f16700Schasinglulu #define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 916*91f16700Schasinglulu #define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 917*91f16700Schasinglulu #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */ 918*91f16700Schasinglulu #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */ 919*91f16700Schasinglulu #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */ 920*91f16700Schasinglulu #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */ 921*91f16700Schasinglulu #define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */ 922*91f16700Schasinglulu #define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 923*91f16700Schasinglulu #define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */ 924*91f16700Schasinglulu /* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */ 925*91f16700Schasinglulu #define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */ 926*91f16700Schasinglulu #define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */ 927*91f16700Schasinglulu #define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */ 928*91f16700Schasinglulu #define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */ 929*91f16700Schasinglulu #define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */ 930*91f16700Schasinglulu #define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */ 931*91f16700Schasinglulu #define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */ 932*91f16700Schasinglulu #define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */ 933*91f16700Schasinglulu #define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */ 934*91f16700Schasinglulu #define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */ 935*91f16700Schasinglulu #define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */ 936*91f16700Schasinglulu #define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */ 937*91f16700Schasinglulu #define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */ 938*91f16700Schasinglulu #define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */ 939*91f16700Schasinglulu #define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */ 940*91f16700Schasinglulu #define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */ 941*91f16700Schasinglulu #define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */ 942*91f16700Schasinglulu #define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */ 943*91f16700Schasinglulu #define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */ 944*91f16700Schasinglulu #define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */ 945*91f16700Schasinglulu #define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */ 946*91f16700Schasinglulu #define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */ 947*91f16700Schasinglulu #define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */ 948*91f16700Schasinglulu #define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */ 949*91f16700Schasinglulu #define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */ 950*91f16700Schasinglulu #define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */ 951*91f16700Schasinglulu #define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */ 952*91f16700Schasinglulu #define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */ 953*91f16700Schasinglulu #define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */ 954*91f16700Schasinglulu #define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */ 955*91f16700Schasinglulu #define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */ 956*91f16700Schasinglulu /* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */ 957*91f16700Schasinglulu #define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 958*91f16700Schasinglulu #define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */ 959*91f16700Schasinglulu #define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */ 960*91f16700Schasinglulu #define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */ 961*91f16700Schasinglulu /* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */ 962*91f16700Schasinglulu #define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */ 963*91f16700Schasinglulu #define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */ 964*91f16700Schasinglulu #define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */ 965*91f16700Schasinglulu #define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */ 966*91f16700Schasinglulu #define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */ 967*91f16700Schasinglulu #define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */ 968*91f16700Schasinglulu /* PCM_REG0_DATA (0x10006000+0x100) */ 969*91f16700Schasinglulu #define PCM_REG0_RF_LSB (1U << 0) /* 32b */ 970*91f16700Schasinglulu /* PCM_REG2_DATA (0x10006000+0x104) */ 971*91f16700Schasinglulu #define PCM_REG2_RF_LSB (1U << 0) /* 32b */ 972*91f16700Schasinglulu /* PCM_REG6_DATA (0x10006000+0x108) */ 973*91f16700Schasinglulu #define PCM_REG6_RF_LSB (1U << 0) /* 32b */ 974*91f16700Schasinglulu /* PCM_REG7_DATA (0x10006000+0x10C) */ 975*91f16700Schasinglulu #define PCM_REG7_RF_LSB (1U << 0) /* 32b */ 976*91f16700Schasinglulu /* PCM_REG13_DATA (0x10006000+0x110) */ 977*91f16700Schasinglulu #define PCM_REG13_RF_LSB (1U << 0) /* 32b */ 978*91f16700Schasinglulu /* SRC_REQ_STA_0 (0x10006000+0x114) */ 979*91f16700Schasinglulu #define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */ 980*91f16700Schasinglulu #define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */ 981*91f16700Schasinglulu #define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */ 982*91f16700Schasinglulu #define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */ 983*91f16700Schasinglulu #define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */ 984*91f16700Schasinglulu #define MD_DDR_EN_0_LSB (1U << 5) /* 1b */ 985*91f16700Schasinglulu #define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */ 986*91f16700Schasinglulu #define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */ 987*91f16700Schasinglulu #define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */ 988*91f16700Schasinglulu #define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */ 989*91f16700Schasinglulu #define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */ 990*91f16700Schasinglulu #define MD_DDR_EN_1_LSB (1U << 11) /* 1b */ 991*91f16700Schasinglulu #define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */ 992*91f16700Schasinglulu #define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */ 993*91f16700Schasinglulu #define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */ 994*91f16700Schasinglulu #define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */ 995*91f16700Schasinglulu #define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */ 996*91f16700Schasinglulu #define CONN_DDR_EN_LSB (1U << 17) /* 1b */ 997*91f16700Schasinglulu #define SRCCLKENI_LSB (1U << 18) /* 3b */ 998*91f16700Schasinglulu #define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */ 999*91f16700Schasinglulu #define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */ 1000*91f16700Schasinglulu #define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */ 1001*91f16700Schasinglulu #define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */ 1002*91f16700Schasinglulu #define MD32_DDR_EN_LSB (1U << 25) /* 1b */ 1003*91f16700Schasinglulu #define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */ 1004*91f16700Schasinglulu #define DISP0_DDR_EN_LSB (1U << 27) /* 1b */ 1005*91f16700Schasinglulu #define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */ 1006*91f16700Schasinglulu #define DISP1_DDR_EN_LSB (1U << 29) /* 1b */ 1007*91f16700Schasinglulu #define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */ 1008*91f16700Schasinglulu /* SRC_REQ_STA_1 (0x10006000+0x118) */ 1009*91f16700Schasinglulu #define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */ 1010*91f16700Schasinglulu #define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */ 1011*91f16700Schasinglulu #define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */ 1012*91f16700Schasinglulu #define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */ 1013*91f16700Schasinglulu #define SCP_DDR_EN_LSB (1U << 4) /* 1b */ 1014*91f16700Schasinglulu #define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */ 1015*91f16700Schasinglulu #define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */ 1016*91f16700Schasinglulu #define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */ 1017*91f16700Schasinglulu #define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */ 1018*91f16700Schasinglulu #define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */ 1019*91f16700Schasinglulu #define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */ 1020*91f16700Schasinglulu #define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */ 1021*91f16700Schasinglulu #define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */ 1022*91f16700Schasinglulu #define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */ 1023*91f16700Schasinglulu #define UFS_DDR_EN_LSB (1U << 14) /* 1b */ 1024*91f16700Schasinglulu #define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */ 1025*91f16700Schasinglulu #define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */ 1026*91f16700Schasinglulu #define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */ 1027*91f16700Schasinglulu #define GCE_DDR_EN_LSB (1U << 18) /* 1b */ 1028*91f16700Schasinglulu #define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */ 1029*91f16700Schasinglulu #define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */ 1030*91f16700Schasinglulu #define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */ 1031*91f16700Schasinglulu #define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */ 1032*91f16700Schasinglulu #define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */ 1033*91f16700Schasinglulu #define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */ 1034*91f16700Schasinglulu #define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */ 1035*91f16700Schasinglulu #define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */ 1036*91f16700Schasinglulu #define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */ 1037*91f16700Schasinglulu #define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */ 1038*91f16700Schasinglulu #define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */ 1039*91f16700Schasinglulu #define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */ 1040*91f16700Schasinglulu /* SRC_REQ_STA_2 (0x10006000+0x11C) */ 1041*91f16700Schasinglulu #define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */ 1042*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */ 1043*91f16700Schasinglulu #define SW2SPM_INT_LSB (1U << 11) /* 4b */ 1044*91f16700Schasinglulu #define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */ 1045*91f16700Schasinglulu #define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */ 1046*91f16700Schasinglulu #define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */ 1047*91f16700Schasinglulu #define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */ 1048*91f16700Schasinglulu #define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */ 1049*91f16700Schasinglulu #define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */ 1050*91f16700Schasinglulu #define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */ 1051*91f16700Schasinglulu #define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */ 1052*91f16700Schasinglulu #define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */ 1053*91f16700Schasinglulu #define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */ 1054*91f16700Schasinglulu #define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */ 1055*91f16700Schasinglulu #define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */ 1056*91f16700Schasinglulu #define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */ 1057*91f16700Schasinglulu /* PCM_TIMER_OUT (0x10006000+0x120) */ 1058*91f16700Schasinglulu #define PCM_TIMER_LSB (1U << 0) /* 32b */ 1059*91f16700Schasinglulu /* PCM_WDT_OUT (0x10006000+0x124) */ 1060*91f16700Schasinglulu #define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */ 1061*91f16700Schasinglulu /* SPM_IRQ_STA (0x10006000+0x128) */ 1062*91f16700Schasinglulu #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 1063*91f16700Schasinglulu #define PCM_IRQ_LSB (1U << 3) /* 1b */ 1064*91f16700Schasinglulu /* SRC_REQ_STA_4 (0x10006000+0x12C) */ 1065*91f16700Schasinglulu #define APU_SRCCLKENA_LSB (1U << 0) /* 1b */ 1066*91f16700Schasinglulu #define APU_INFRA_REQ_LSB (1U << 1) /* 1b */ 1067*91f16700Schasinglulu #define APU_APSRC_REQ_LSB (1U << 2) /* 1b */ 1068*91f16700Schasinglulu #define APU_VRF18_REQ_LSB (1U << 3) /* 1b */ 1069*91f16700Schasinglulu #define APU_DDR_EN_LSB (1U << 4) /* 1b */ 1070*91f16700Schasinglulu #define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */ 1071*91f16700Schasinglulu #define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */ 1072*91f16700Schasinglulu #define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */ 1073*91f16700Schasinglulu #define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */ 1074*91f16700Schasinglulu #define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */ 1075*91f16700Schasinglulu /* MD32PCM_WAKEUP_STA (0x10006000+0x130) */ 1076*91f16700Schasinglulu #define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */ 1077*91f16700Schasinglulu /* MD32PCM_EVENT_STA (0x10006000+0x134) */ 1078*91f16700Schasinglulu #define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */ 1079*91f16700Schasinglulu /* SPM_WAKEUP_STA (0x10006000+0x138) */ 1080*91f16700Schasinglulu #define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */ 1081*91f16700Schasinglulu #define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */ 1082*91f16700Schasinglulu /* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */ 1083*91f16700Schasinglulu #define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */ 1084*91f16700Schasinglulu /* SPM_WAKEUP_MISC (0x10006000+0x140) */ 1085*91f16700Schasinglulu #define GIC_WAKEUP_LSB (1U << 0) /* 10b */ 1086*91f16700Schasinglulu #define DVFSRC_IRQ_LSB (1U << 16) /* 1b */ 1087*91f16700Schasinglulu #define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */ 1088*91f16700Schasinglulu #define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */ 1089*91f16700Schasinglulu #define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */ 1090*91f16700Schasinglulu #define TWAM_IRQ_B_LSB (1U << 21) /* 1b */ 1091*91f16700Schasinglulu #define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */ 1092*91f16700Schasinglulu #define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */ 1093*91f16700Schasinglulu #define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */ 1094*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */ 1095*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */ 1096*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */ 1097*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */ 1098*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */ 1099*91f16700Schasinglulu #define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */ 1100*91f16700Schasinglulu #define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */ 1101*91f16700Schasinglulu /* MM_DVFS_HALT (0x10006000+0x144) */ 1102*91f16700Schasinglulu #define MM_DVFS_HALT_LSB (1U << 0) /* 5b */ 1103*91f16700Schasinglulu /* BUS_PROTECT_RDY (0x10006000+0x150) */ 1104*91f16700Schasinglulu #define PROTECT_READY_LSB (1U << 0) /* 32b */ 1105*91f16700Schasinglulu /* BUS_PROTECT1_RDY (0x10006000+0x154) */ 1106*91f16700Schasinglulu #define PROTECT1_READY_LSB (1U << 0) /* 32b */ 1107*91f16700Schasinglulu /* BUS_PROTECT2_RDY (0x10006000+0x158) */ 1108*91f16700Schasinglulu #define PROTECT2_READY_LSB (1U << 0) /* 32b */ 1109*91f16700Schasinglulu /* BUS_PROTECT3_RDY (0x10006000+0x15C) */ 1110*91f16700Schasinglulu #define PROTECT3_READY_LSB (1U << 0) /* 32b */ 1111*91f16700Schasinglulu /* SUBSYS_IDLE_STA (0x10006000+0x160) */ 1112*91f16700Schasinglulu #define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */ 1113*91f16700Schasinglulu /* PCM_STA (0x10006000+0x164) */ 1114*91f16700Schasinglulu #define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */ 1115*91f16700Schasinglulu #define EXT_SRC_STA_LSB (1U << 4) /* 3b */ 1116*91f16700Schasinglulu /* SRC_REQ_STA_3 (0x10006000+0x168) */ 1117*91f16700Schasinglulu #define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */ 1118*91f16700Schasinglulu #define F26M_STATE_LSB (1U << 16) /* 1b */ 1119*91f16700Schasinglulu #define INFRA_STATE_LSB (1U << 17) /* 1b */ 1120*91f16700Schasinglulu #define APSRC_STATE_LSB (1U << 18) /* 1b */ 1121*91f16700Schasinglulu #define VRF18_STATE_LSB (1U << 19) /* 1b */ 1122*91f16700Schasinglulu #define DDR_EN_STATE_LSB (1U << 20) /* 1b */ 1123*91f16700Schasinglulu #define DVFS_STATE_LSB (1U << 21) /* 1b */ 1124*91f16700Schasinglulu #define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */ 1125*91f16700Schasinglulu #define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */ 1126*91f16700Schasinglulu #define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */ 1127*91f16700Schasinglulu #define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */ 1128*91f16700Schasinglulu /* PWR_STATUS (0x10006000+0x16C) */ 1129*91f16700Schasinglulu #define PWR_STATUS_LSB (1U << 0) /* 32b */ 1130*91f16700Schasinglulu /* PWR_STATUS_2ND (0x10006000+0x170) */ 1131*91f16700Schasinglulu #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 1132*91f16700Schasinglulu /* CPU_PWR_STATUS (0x10006000+0x174) */ 1133*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */ 1134*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */ 1135*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */ 1136*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */ 1137*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */ 1138*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */ 1139*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */ 1140*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */ 1141*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */ 1142*91f16700Schasinglulu #define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */ 1143*91f16700Schasinglulu /* OTHER_PWR_STATUS (0x10006000+0x178) */ 1144*91f16700Schasinglulu #define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */ 1145*91f16700Schasinglulu /* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */ 1146*91f16700Schasinglulu #define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1147*91f16700Schasinglulu #define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1148*91f16700Schasinglulu /* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */ 1149*91f16700Schasinglulu #define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1150*91f16700Schasinglulu #define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1151*91f16700Schasinglulu /* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */ 1152*91f16700Schasinglulu #define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1153*91f16700Schasinglulu #define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1154*91f16700Schasinglulu /* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */ 1155*91f16700Schasinglulu #define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1156*91f16700Schasinglulu #define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1157*91f16700Schasinglulu /* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */ 1158*91f16700Schasinglulu #define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */ 1159*91f16700Schasinglulu #define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */ 1160*91f16700Schasinglulu /* MD32PCM_STA (0x10006000+0x190) */ 1161*91f16700Schasinglulu #define MD32PCM_HALT_LSB (1U << 0) /* 1b */ 1162*91f16700Schasinglulu #define MD32PCM_GATED_LSB (1U << 1) /* 1b */ 1163*91f16700Schasinglulu /* MD32PCM_PC (0x10006000+0x194) */ 1164*91f16700Schasinglulu #define MON_PC_LSB (1U << 0) /* 32b */ 1165*91f16700Schasinglulu /* DVFSRC_EVENT_STA (0x10006000+0x1A4) */ 1166*91f16700Schasinglulu #define DVFSRC_EVENT_LSB (1U << 0) /* 32b */ 1167*91f16700Schasinglulu /* BUS_PROTECT4_RDY (0x10006000+0x1A8) */ 1168*91f16700Schasinglulu #define PROTECT4_READY_LSB (1U << 0) /* 32b */ 1169*91f16700Schasinglulu /* BUS_PROTECT5_RDY (0x10006000+0x1AC) */ 1170*91f16700Schasinglulu #define PROTECT5_READY_LSB (1U << 0) /* 32b */ 1171*91f16700Schasinglulu /* BUS_PROTECT6_RDY (0x10006000+0x1B0) */ 1172*91f16700Schasinglulu #define PROTECT6_READY_LSB (1U << 0) /* 32b */ 1173*91f16700Schasinglulu /* BUS_PROTECT7_RDY (0x10006000+0x1B4) */ 1174*91f16700Schasinglulu #define PROTECT7_READY_LSB (1U << 0) /* 32b */ 1175*91f16700Schasinglulu /* BUS_PROTECT8_RDY (0x10006000+0x1B8) */ 1176*91f16700Schasinglulu #define PROTECT8_READY_LSB (1U << 0) /* 32b */ 1177*91f16700Schasinglulu /* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */ 1178*91f16700Schasinglulu #define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1179*91f16700Schasinglulu /* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */ 1180*91f16700Schasinglulu #define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1181*91f16700Schasinglulu /* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */ 1182*91f16700Schasinglulu #define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1183*91f16700Schasinglulu /* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */ 1184*91f16700Schasinglulu #define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1185*91f16700Schasinglulu /* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */ 1186*91f16700Schasinglulu #define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */ 1187*91f16700Schasinglulu /* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */ 1188*91f16700Schasinglulu #define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */ 1189*91f16700Schasinglulu /* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */ 1190*91f16700Schasinglulu #define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */ 1191*91f16700Schasinglulu /* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */ 1192*91f16700Schasinglulu #define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */ 1193*91f16700Schasinglulu /* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */ 1194*91f16700Schasinglulu #define TWAM_TIMER_LSB (1U << 0) /* 32b */ 1195*91f16700Schasinglulu /* SPM_CG_CHECK_STA (0x10006000+0x1F4) */ 1196*91f16700Schasinglulu #define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */ 1197*91f16700Schasinglulu #define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */ 1198*91f16700Schasinglulu #define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */ 1199*91f16700Schasinglulu /* SPM_DVFS_STA (0x10006000+0x1F8) */ 1200*91f16700Schasinglulu #define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1201*91f16700Schasinglulu /* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */ 1202*91f16700Schasinglulu #define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */ 1203*91f16700Schasinglulu #define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */ 1204*91f16700Schasinglulu #define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */ 1205*91f16700Schasinglulu /* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */ 1206*91f16700Schasinglulu #define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1207*91f16700Schasinglulu #define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */ 1208*91f16700Schasinglulu #define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1209*91f16700Schasinglulu #define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */ 1210*91f16700Schasinglulu #define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */ 1211*91f16700Schasinglulu #define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1212*91f16700Schasinglulu #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */ 1213*91f16700Schasinglulu /* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */ 1214*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */ 1215*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */ 1216*91f16700Schasinglulu #define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */ 1217*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */ 1218*91f16700Schasinglulu #define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */ 1219*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */ 1220*91f16700Schasinglulu #define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */ 1221*91f16700Schasinglulu #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */ 1222*91f16700Schasinglulu /* SPM_CPU0_PWR_CON (0x10006000+0x208) */ 1223*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */ 1224*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */ 1225*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */ 1226*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */ 1227*91f16700Schasinglulu #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */ 1228*91f16700Schasinglulu /* SPM_CPU1_PWR_CON (0x10006000+0x20C) */ 1229*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */ 1230*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */ 1231*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */ 1232*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */ 1233*91f16700Schasinglulu #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */ 1234*91f16700Schasinglulu /* SPM_CPU2_PWR_CON (0x10006000+0x210) */ 1235*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */ 1236*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */ 1237*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */ 1238*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */ 1239*91f16700Schasinglulu #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */ 1240*91f16700Schasinglulu /* SPM_CPU3_PWR_CON (0x10006000+0x214) */ 1241*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */ 1242*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */ 1243*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */ 1244*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */ 1245*91f16700Schasinglulu #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */ 1246*91f16700Schasinglulu /* SPM_CPU4_PWR_CON (0x10006000+0x218) */ 1247*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */ 1248*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */ 1249*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */ 1250*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */ 1251*91f16700Schasinglulu #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */ 1252*91f16700Schasinglulu /* SPM_CPU5_PWR_CON (0x10006000+0x21C) */ 1253*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */ 1254*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */ 1255*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */ 1256*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */ 1257*91f16700Schasinglulu #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */ 1258*91f16700Schasinglulu /* SPM_CPU6_PWR_CON (0x10006000+0x220) */ 1259*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */ 1260*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */ 1261*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */ 1262*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */ 1263*91f16700Schasinglulu #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */ 1264*91f16700Schasinglulu /* SPM_CPU7_PWR_CON (0x10006000+0x224) */ 1265*91f16700Schasinglulu #define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */ 1266*91f16700Schasinglulu #define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */ 1267*91f16700Schasinglulu #define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */ 1268*91f16700Schasinglulu #define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */ 1269*91f16700Schasinglulu #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */ 1270*91f16700Schasinglulu /* ARMPLL_CLK_CON (0x10006000+0x22C) */ 1271*91f16700Schasinglulu #define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */ 1272*91f16700Schasinglulu #define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */ 1273*91f16700Schasinglulu #define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */ 1274*91f16700Schasinglulu #define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */ 1275*91f16700Schasinglulu #define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */ 1276*91f16700Schasinglulu #define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */ 1277*91f16700Schasinglulu #define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */ 1278*91f16700Schasinglulu #define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */ 1279*91f16700Schasinglulu #define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */ 1280*91f16700Schasinglulu #define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */ 1281*91f16700Schasinglulu #define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */ 1282*91f16700Schasinglulu #define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */ 1283*91f16700Schasinglulu #define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */ 1284*91f16700Schasinglulu #define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */ 1285*91f16700Schasinglulu #define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */ 1286*91f16700Schasinglulu #define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */ 1287*91f16700Schasinglulu #define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */ 1288*91f16700Schasinglulu #define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */ 1289*91f16700Schasinglulu #define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */ 1290*91f16700Schasinglulu #define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */ 1291*91f16700Schasinglulu /* MCUSYS_IDLE_STA (0x10006000+0x230) */ 1292*91f16700Schasinglulu #define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */ 1293*91f16700Schasinglulu #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */ 1294*91f16700Schasinglulu #define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */ 1295*91f16700Schasinglulu #define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */ 1296*91f16700Schasinglulu #define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */ 1297*91f16700Schasinglulu #define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */ 1298*91f16700Schasinglulu #define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */ 1299*91f16700Schasinglulu #define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */ 1300*91f16700Schasinglulu #define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */ 1301*91f16700Schasinglulu #define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */ 1302*91f16700Schasinglulu #define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */ 1303*91f16700Schasinglulu #define WFI_AF_SEL_LSB (1U << 24) /* 8b */ 1304*91f16700Schasinglulu /* GIC_WAKEUP_STA (0x10006000+0x234) */ 1305*91f16700Schasinglulu #define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */ 1306*91f16700Schasinglulu /* CPU_SPARE_CON (0x10006000+0x238) */ 1307*91f16700Schasinglulu #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 1308*91f16700Schasinglulu /* CPU_SPARE_CON_SET (0x10006000+0x23C) */ 1309*91f16700Schasinglulu #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1310*91f16700Schasinglulu /* CPU_SPARE_CON_CLR (0x10006000+0x240) */ 1311*91f16700Schasinglulu #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1312*91f16700Schasinglulu /* ARMPLL_CLK_SEL (0x10006000+0x244) */ 1313*91f16700Schasinglulu #define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */ 1314*91f16700Schasinglulu /* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */ 1315*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */ 1316*91f16700Schasinglulu /* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */ 1317*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */ 1318*91f16700Schasinglulu /* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */ 1319*91f16700Schasinglulu #define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */ 1320*91f16700Schasinglulu /* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */ 1321*91f16700Schasinglulu #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1322*91f16700Schasinglulu #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ 1323*91f16700Schasinglulu /* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */ 1324*91f16700Schasinglulu #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1325*91f16700Schasinglulu #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ 1326*91f16700Schasinglulu /* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */ 1327*91f16700Schasinglulu #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1328*91f16700Schasinglulu #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ 1329*91f16700Schasinglulu /* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */ 1330*91f16700Schasinglulu #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1331*91f16700Schasinglulu #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ 1332*91f16700Schasinglulu /* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */ 1333*91f16700Schasinglulu #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1334*91f16700Schasinglulu #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ 1335*91f16700Schasinglulu /* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */ 1336*91f16700Schasinglulu #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1337*91f16700Schasinglulu #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ 1338*91f16700Schasinglulu /* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */ 1339*91f16700Schasinglulu #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1340*91f16700Schasinglulu #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ 1341*91f16700Schasinglulu /* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */ 1342*91f16700Schasinglulu #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1343*91f16700Schasinglulu #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ 1344*91f16700Schasinglulu /* MP0_CPU0_WFI_EN (0x10006000+0x280) */ 1345*91f16700Schasinglulu #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1346*91f16700Schasinglulu /* MP0_CPU1_WFI_EN (0x10006000+0x284) */ 1347*91f16700Schasinglulu #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1348*91f16700Schasinglulu /* MP0_CPU2_WFI_EN (0x10006000+0x288) */ 1349*91f16700Schasinglulu #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1350*91f16700Schasinglulu /* MP0_CPU3_WFI_EN (0x10006000+0x28C) */ 1351*91f16700Schasinglulu #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1352*91f16700Schasinglulu /* MP0_CPU4_WFI_EN (0x10006000+0x290) */ 1353*91f16700Schasinglulu #define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */ 1354*91f16700Schasinglulu /* MP0_CPU5_WFI_EN (0x10006000+0x294) */ 1355*91f16700Schasinglulu #define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */ 1356*91f16700Schasinglulu /* MP0_CPU6_WFI_EN (0x10006000+0x298) */ 1357*91f16700Schasinglulu #define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */ 1358*91f16700Schasinglulu /* MP0_CPU7_WFI_EN (0x10006000+0x29C) */ 1359*91f16700Schasinglulu #define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */ 1360*91f16700Schasinglulu /* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */ 1361*91f16700Schasinglulu #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 1362*91f16700Schasinglulu /* ROOT_CORE_ADDR (0x10006000+0x2A4) */ 1363*91f16700Schasinglulu #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 1364*91f16700Schasinglulu /* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */ 1365*91f16700Schasinglulu #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 1366*91f16700Schasinglulu /* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */ 1367*91f16700Schasinglulu #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 1368*91f16700Schasinglulu /* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */ 1369*91f16700Schasinglulu #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 1370*91f16700Schasinglulu /* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */ 1371*91f16700Schasinglulu #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 1372*91f16700Schasinglulu /* SW2SPM_INT (0x10006000+0x2E0) */ 1373*91f16700Schasinglulu #define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */ 1374*91f16700Schasinglulu /* SW2SPM_INT_SET (0x10006000+0x2E4) */ 1375*91f16700Schasinglulu #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1376*91f16700Schasinglulu /* SW2SPM_INT_CLR (0x10006000+0x2E8) */ 1377*91f16700Schasinglulu #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1378*91f16700Schasinglulu /* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */ 1379*91f16700Schasinglulu #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1380*91f16700Schasinglulu /* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */ 1381*91f16700Schasinglulu #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1382*91f16700Schasinglulu /* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */ 1383*91f16700Schasinglulu #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1384*91f16700Schasinglulu /* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */ 1385*91f16700Schasinglulu #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1386*91f16700Schasinglulu /* SW2SPM_CFG (0x10006000+0x2FC) */ 1387*91f16700Schasinglulu #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1388*91f16700Schasinglulu /* MD1_PWR_CON (0x10006000+0x300) */ 1389*91f16700Schasinglulu #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1390*91f16700Schasinglulu #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 1391*91f16700Schasinglulu #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 1392*91f16700Schasinglulu #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1393*91f16700Schasinglulu #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1394*91f16700Schasinglulu #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1395*91f16700Schasinglulu #define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1396*91f16700Schasinglulu /* CONN_PWR_CON (0x10006000+0x304) */ 1397*91f16700Schasinglulu #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1398*91f16700Schasinglulu #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 1399*91f16700Schasinglulu #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 1400*91f16700Schasinglulu #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1401*91f16700Schasinglulu #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1402*91f16700Schasinglulu /* MFG0_PWR_CON (0x10006000+0x308) */ 1403*91f16700Schasinglulu #define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1404*91f16700Schasinglulu #define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */ 1405*91f16700Schasinglulu #define MFG0_PWR_ON_LSB (1U << 2) /* 1b */ 1406*91f16700Schasinglulu #define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1407*91f16700Schasinglulu #define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1408*91f16700Schasinglulu #define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */ 1409*91f16700Schasinglulu #define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1410*91f16700Schasinglulu /* MFG1_PWR_CON (0x10006000+0x30C) */ 1411*91f16700Schasinglulu #define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1412*91f16700Schasinglulu #define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */ 1413*91f16700Schasinglulu #define MFG1_PWR_ON_LSB (1U << 2) /* 1b */ 1414*91f16700Schasinglulu #define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1415*91f16700Schasinglulu #define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1416*91f16700Schasinglulu #define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1417*91f16700Schasinglulu #define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1418*91f16700Schasinglulu /* MFG2_PWR_CON (0x10006000+0x310) */ 1419*91f16700Schasinglulu #define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1420*91f16700Schasinglulu #define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */ 1421*91f16700Schasinglulu #define MFG2_PWR_ON_LSB (1U << 2) /* 1b */ 1422*91f16700Schasinglulu #define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1423*91f16700Schasinglulu #define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1424*91f16700Schasinglulu #define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1425*91f16700Schasinglulu #define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1426*91f16700Schasinglulu /* MFG3_PWR_CON (0x10006000+0x314) */ 1427*91f16700Schasinglulu #define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */ 1428*91f16700Schasinglulu #define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */ 1429*91f16700Schasinglulu #define MFG3_PWR_ON_LSB (1U << 2) /* 1b */ 1430*91f16700Schasinglulu #define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1431*91f16700Schasinglulu #define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1432*91f16700Schasinglulu #define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */ 1433*91f16700Schasinglulu #define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1434*91f16700Schasinglulu /* MFG4_PWR_CON (0x10006000+0x318) */ 1435*91f16700Schasinglulu #define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */ 1436*91f16700Schasinglulu #define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */ 1437*91f16700Schasinglulu #define MFG4_PWR_ON_LSB (1U << 2) /* 1b */ 1438*91f16700Schasinglulu #define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1439*91f16700Schasinglulu #define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1440*91f16700Schasinglulu #define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */ 1441*91f16700Schasinglulu #define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1442*91f16700Schasinglulu /* MFG5_PWR_CON (0x10006000+0x31C) */ 1443*91f16700Schasinglulu #define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */ 1444*91f16700Schasinglulu #define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */ 1445*91f16700Schasinglulu #define MFG5_PWR_ON_LSB (1U << 2) /* 1b */ 1446*91f16700Schasinglulu #define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1447*91f16700Schasinglulu #define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1448*91f16700Schasinglulu #define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */ 1449*91f16700Schasinglulu #define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1450*91f16700Schasinglulu /* MFG6_PWR_CON (0x10006000+0x320) */ 1451*91f16700Schasinglulu #define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */ 1452*91f16700Schasinglulu #define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */ 1453*91f16700Schasinglulu #define MFG6_PWR_ON_LSB (1U << 2) /* 1b */ 1454*91f16700Schasinglulu #define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1455*91f16700Schasinglulu #define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1456*91f16700Schasinglulu #define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */ 1457*91f16700Schasinglulu #define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1458*91f16700Schasinglulu /* IFR_PWR_CON (0x10006000+0x324) */ 1459*91f16700Schasinglulu #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 1460*91f16700Schasinglulu #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 1461*91f16700Schasinglulu #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 1462*91f16700Schasinglulu #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1463*91f16700Schasinglulu #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1464*91f16700Schasinglulu #define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */ 1465*91f16700Schasinglulu #define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1466*91f16700Schasinglulu /* IFR_SUB_PWR_CON (0x10006000+0x328) */ 1467*91f16700Schasinglulu #define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1468*91f16700Schasinglulu #define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */ 1469*91f16700Schasinglulu #define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */ 1470*91f16700Schasinglulu #define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1471*91f16700Schasinglulu #define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1472*91f16700Schasinglulu #define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1473*91f16700Schasinglulu #define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1474*91f16700Schasinglulu /* DPY_PWR_CON (0x10006000+0x32C) */ 1475*91f16700Schasinglulu #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 1476*91f16700Schasinglulu #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 1477*91f16700Schasinglulu #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 1478*91f16700Schasinglulu #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1479*91f16700Schasinglulu #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1480*91f16700Schasinglulu #define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */ 1481*91f16700Schasinglulu #define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1482*91f16700Schasinglulu /* ISP_PWR_CON (0x10006000+0x330) */ 1483*91f16700Schasinglulu #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1484*91f16700Schasinglulu #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 1485*91f16700Schasinglulu #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 1486*91f16700Schasinglulu #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1487*91f16700Schasinglulu #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1488*91f16700Schasinglulu #define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1489*91f16700Schasinglulu #define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1490*91f16700Schasinglulu /* ISP2_PWR_CON (0x10006000+0x334) */ 1491*91f16700Schasinglulu #define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1492*91f16700Schasinglulu #define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */ 1493*91f16700Schasinglulu #define ISP2_PWR_ON_LSB (1U << 2) /* 1b */ 1494*91f16700Schasinglulu #define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1495*91f16700Schasinglulu #define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1496*91f16700Schasinglulu #define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1497*91f16700Schasinglulu #define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1498*91f16700Schasinglulu /* IPE_PWR_CON (0x10006000+0x338) */ 1499*91f16700Schasinglulu #define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1500*91f16700Schasinglulu #define IPE_PWR_ISO_LSB (1U << 1) /* 1b */ 1501*91f16700Schasinglulu #define IPE_PWR_ON_LSB (1U << 2) /* 1b */ 1502*91f16700Schasinglulu #define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1503*91f16700Schasinglulu #define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1504*91f16700Schasinglulu #define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1505*91f16700Schasinglulu #define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1506*91f16700Schasinglulu /* VDE_PWR_CON (0x10006000+0x33C) */ 1507*91f16700Schasinglulu #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1508*91f16700Schasinglulu #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 1509*91f16700Schasinglulu #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 1510*91f16700Schasinglulu #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1511*91f16700Schasinglulu #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1512*91f16700Schasinglulu #define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */ 1513*91f16700Schasinglulu #define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1514*91f16700Schasinglulu /* VDE2_PWR_CON (0x10006000+0x340) */ 1515*91f16700Schasinglulu #define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1516*91f16700Schasinglulu #define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */ 1517*91f16700Schasinglulu #define VDE2_PWR_ON_LSB (1U << 2) /* 1b */ 1518*91f16700Schasinglulu #define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1519*91f16700Schasinglulu #define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1520*91f16700Schasinglulu #define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1521*91f16700Schasinglulu #define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1522*91f16700Schasinglulu /* VEN_PWR_CON (0x10006000+0x344) */ 1523*91f16700Schasinglulu #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1524*91f16700Schasinglulu #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 1525*91f16700Schasinglulu #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 1526*91f16700Schasinglulu #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1527*91f16700Schasinglulu #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1528*91f16700Schasinglulu #define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */ 1529*91f16700Schasinglulu #define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1530*91f16700Schasinglulu /* VEN_CORE1_PWR_CON (0x10006000+0x348) */ 1531*91f16700Schasinglulu #define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1532*91f16700Schasinglulu #define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1533*91f16700Schasinglulu #define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1534*91f16700Schasinglulu #define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1535*91f16700Schasinglulu #define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1536*91f16700Schasinglulu #define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1537*91f16700Schasinglulu #define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1538*91f16700Schasinglulu /* MDP_PWR_CON (0x10006000+0x34C) */ 1539*91f16700Schasinglulu #define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1540*91f16700Schasinglulu #define MDP_PWR_ISO_LSB (1U << 1) /* 1b */ 1541*91f16700Schasinglulu #define MDP_PWR_ON_LSB (1U << 2) /* 1b */ 1542*91f16700Schasinglulu #define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1543*91f16700Schasinglulu #define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1544*91f16700Schasinglulu #define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1545*91f16700Schasinglulu #define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1546*91f16700Schasinglulu /* DIS_PWR_CON (0x10006000+0x350) */ 1547*91f16700Schasinglulu #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 1548*91f16700Schasinglulu #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 1549*91f16700Schasinglulu #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 1550*91f16700Schasinglulu #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1551*91f16700Schasinglulu #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1552*91f16700Schasinglulu #define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */ 1553*91f16700Schasinglulu #define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1554*91f16700Schasinglulu /* AUDIO_PWR_CON (0x10006000+0x354) */ 1555*91f16700Schasinglulu #define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */ 1556*91f16700Schasinglulu #define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */ 1557*91f16700Schasinglulu #define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */ 1558*91f16700Schasinglulu #define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1559*91f16700Schasinglulu #define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1560*91f16700Schasinglulu #define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */ 1561*91f16700Schasinglulu #define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1562*91f16700Schasinglulu /* ADSP_PWR_CON (0x10006000+0x358) */ 1563*91f16700Schasinglulu #define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1564*91f16700Schasinglulu #define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */ 1565*91f16700Schasinglulu #define ADSP_PWR_ON_LSB (1U << 2) /* 1b */ 1566*91f16700Schasinglulu #define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1567*91f16700Schasinglulu #define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1568*91f16700Schasinglulu #define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1569*91f16700Schasinglulu #define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1570*91f16700Schasinglulu #define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */ 1571*91f16700Schasinglulu #define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */ 1572*91f16700Schasinglulu #define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1573*91f16700Schasinglulu #define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */ 1574*91f16700Schasinglulu /* CAM_PWR_CON (0x10006000+0x35C) */ 1575*91f16700Schasinglulu #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1576*91f16700Schasinglulu #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 1577*91f16700Schasinglulu #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 1578*91f16700Schasinglulu #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1579*91f16700Schasinglulu #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1580*91f16700Schasinglulu #define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */ 1581*91f16700Schasinglulu #define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1582*91f16700Schasinglulu /* CAM_RAWA_PWR_CON (0x10006000+0x360) */ 1583*91f16700Schasinglulu #define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */ 1584*91f16700Schasinglulu #define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */ 1585*91f16700Schasinglulu #define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */ 1586*91f16700Schasinglulu #define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1587*91f16700Schasinglulu #define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1588*91f16700Schasinglulu #define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */ 1589*91f16700Schasinglulu #define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1590*91f16700Schasinglulu /* CAM_RAWB_PWR_CON (0x10006000+0x364) */ 1591*91f16700Schasinglulu #define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */ 1592*91f16700Schasinglulu #define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */ 1593*91f16700Schasinglulu #define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */ 1594*91f16700Schasinglulu #define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1595*91f16700Schasinglulu #define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1596*91f16700Schasinglulu #define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */ 1597*91f16700Schasinglulu #define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1598*91f16700Schasinglulu /* CAM_RAWC_PWR_CON (0x10006000+0x368) */ 1599*91f16700Schasinglulu #define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1600*91f16700Schasinglulu #define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */ 1601*91f16700Schasinglulu #define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */ 1602*91f16700Schasinglulu #define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1603*91f16700Schasinglulu #define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1604*91f16700Schasinglulu #define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */ 1605*91f16700Schasinglulu #define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1606*91f16700Schasinglulu /* SYSRAM_CON (0x10006000+0x36C) */ 1607*91f16700Schasinglulu #define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1608*91f16700Schasinglulu #define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1609*91f16700Schasinglulu #define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */ 1610*91f16700Schasinglulu #define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */ 1611*91f16700Schasinglulu /* SYSROM_CON (0x10006000+0x370) */ 1612*91f16700Schasinglulu #define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */ 1613*91f16700Schasinglulu /* SSPM_SRAM_CON (0x10006000+0x374) */ 1614*91f16700Schasinglulu #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1615*91f16700Schasinglulu #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1616*91f16700Schasinglulu #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1617*91f16700Schasinglulu #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1618*91f16700Schasinglulu /* SCP_SRAM_CON (0x10006000+0x378) */ 1619*91f16700Schasinglulu #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1620*91f16700Schasinglulu #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1621*91f16700Schasinglulu #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1622*91f16700Schasinglulu #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1623*91f16700Schasinglulu /* DPY_SHU_SRAM_CON (0x10006000+0x37C) */ 1624*91f16700Schasinglulu #define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1625*91f16700Schasinglulu #define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1626*91f16700Schasinglulu #define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1627*91f16700Schasinglulu #define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */ 1628*91f16700Schasinglulu /* UFS_SRAM_CON (0x10006000+0x380) */ 1629*91f16700Schasinglulu #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1630*91f16700Schasinglulu #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1631*91f16700Schasinglulu #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1632*91f16700Schasinglulu #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ 1633*91f16700Schasinglulu /* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */ 1634*91f16700Schasinglulu #define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1635*91f16700Schasinglulu #define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1636*91f16700Schasinglulu #define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1637*91f16700Schasinglulu #define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1638*91f16700Schasinglulu /* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */ 1639*91f16700Schasinglulu #define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1640*91f16700Schasinglulu #define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1641*91f16700Schasinglulu #define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1642*91f16700Schasinglulu #define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */ 1643*91f16700Schasinglulu /* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */ 1644*91f16700Schasinglulu #define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1645*91f16700Schasinglulu #define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1646*91f16700Schasinglulu #define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */ 1647*91f16700Schasinglulu #define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */ 1648*91f16700Schasinglulu /* USB_SRAM_CON (0x10006000+0x390) */ 1649*91f16700Schasinglulu #define USB_SRAM_PDN_LSB (1U << 0) /* 7b */ 1650*91f16700Schasinglulu /* DUMMY_SRAM_CON (0x10006000+0x394) */ 1651*91f16700Schasinglulu #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1652*91f16700Schasinglulu #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1653*91f16700Schasinglulu #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1654*91f16700Schasinglulu #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ 1655*91f16700Schasinglulu /* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */ 1656*91f16700Schasinglulu #define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1657*91f16700Schasinglulu #define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1658*91f16700Schasinglulu /* EXT_BUCK_ISO (0x10006000+0x39C) */ 1659*91f16700Schasinglulu #define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1660*91f16700Schasinglulu #define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1661*91f16700Schasinglulu #define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */ 1662*91f16700Schasinglulu /* DXCC_SRAM_CON (0x10006000+0x3A0) */ 1663*91f16700Schasinglulu #define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1664*91f16700Schasinglulu #define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1665*91f16700Schasinglulu #define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1666*91f16700Schasinglulu #define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */ 1667*91f16700Schasinglulu /* MSDC_SRAM_CON (0x10006000+0x3A4) */ 1668*91f16700Schasinglulu #define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1669*91f16700Schasinglulu #define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1670*91f16700Schasinglulu #define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1671*91f16700Schasinglulu #define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */ 1672*91f16700Schasinglulu /* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */ 1673*91f16700Schasinglulu #define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */ 1674*91f16700Schasinglulu /* DP_TX_PWR_CON (0x10006000+0x3AC) */ 1675*91f16700Schasinglulu #define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */ 1676*91f16700Schasinglulu #define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */ 1677*91f16700Schasinglulu #define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */ 1678*91f16700Schasinglulu #define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1679*91f16700Schasinglulu #define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1680*91f16700Schasinglulu #define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */ 1681*91f16700Schasinglulu #define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1682*91f16700Schasinglulu /* DPMAIF_SRAM_CON (0x10006000+0x3B0) */ 1683*91f16700Schasinglulu #define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1684*91f16700Schasinglulu #define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1685*91f16700Schasinglulu #define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1686*91f16700Schasinglulu #define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */ 1687*91f16700Schasinglulu /* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */ 1688*91f16700Schasinglulu #define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1689*91f16700Schasinglulu #define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1690*91f16700Schasinglulu #define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */ 1691*91f16700Schasinglulu #define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */ 1692*91f16700Schasinglulu /* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */ 1693*91f16700Schasinglulu #define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1694*91f16700Schasinglulu #define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1695*91f16700Schasinglulu #define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1696*91f16700Schasinglulu #define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */ 1697*91f16700Schasinglulu /* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */ 1698*91f16700Schasinglulu #define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1699*91f16700Schasinglulu #define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1700*91f16700Schasinglulu #define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1701*91f16700Schasinglulu #define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */ 1702*91f16700Schasinglulu /* MCUPM_SRAM_CON (0x10006000+0x3C0) */ 1703*91f16700Schasinglulu #define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1704*91f16700Schasinglulu #define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1705*91f16700Schasinglulu #define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1706*91f16700Schasinglulu #define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */ 1707*91f16700Schasinglulu /* DPY2_PWR_CON (0x10006000+0x3C4) */ 1708*91f16700Schasinglulu #define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1709*91f16700Schasinglulu #define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */ 1710*91f16700Schasinglulu #define DPY2_PWR_ON_LSB (1U << 2) /* 1b */ 1711*91f16700Schasinglulu #define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1712*91f16700Schasinglulu #define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1713*91f16700Schasinglulu #define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */ 1714*91f16700Schasinglulu #define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1715*91f16700Schasinglulu /* SPM_MEM_CK_SEL (0x10006000+0x400) */ 1716*91f16700Schasinglulu #define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */ 1717*91f16700Schasinglulu #define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */ 1718*91f16700Schasinglulu /* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */ 1719*91f16700Schasinglulu #define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */ 1720*91f16700Schasinglulu /* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */ 1721*91f16700Schasinglulu #define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */ 1722*91f16700Schasinglulu /* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */ 1723*91f16700Schasinglulu #define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */ 1724*91f16700Schasinglulu /* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */ 1725*91f16700Schasinglulu #define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */ 1726*91f16700Schasinglulu /* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */ 1727*91f16700Schasinglulu #define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */ 1728*91f16700Schasinglulu /* SPM_EMI_BW_MODE (0x10006000+0x418) */ 1729*91f16700Schasinglulu #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1730*91f16700Schasinglulu #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1731*91f16700Schasinglulu #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1732*91f16700Schasinglulu #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1733*91f16700Schasinglulu /* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */ 1734*91f16700Schasinglulu #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1735*91f16700Schasinglulu /* ULPOSC_CON (0x10006000+0x420) */ 1736*91f16700Schasinglulu #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1737*91f16700Schasinglulu #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1738*91f16700Schasinglulu #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1739*91f16700Schasinglulu #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1740*91f16700Schasinglulu /* SPM2MM_CON (0x10006000+0x424) */ 1741*91f16700Schasinglulu #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1742*91f16700Schasinglulu #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1743*91f16700Schasinglulu #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1744*91f16700Schasinglulu #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1745*91f16700Schasinglulu #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1746*91f16700Schasinglulu #define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */ 1747*91f16700Schasinglulu #define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */ 1748*91f16700Schasinglulu #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1749*91f16700Schasinglulu #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1750*91f16700Schasinglulu #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1751*91f16700Schasinglulu /* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */ 1752*91f16700Schasinglulu #define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */ 1753*91f16700Schasinglulu /* SPM2MCUPM_CON (0x10006000+0x42C) */ 1754*91f16700Schasinglulu #define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */ 1755*91f16700Schasinglulu #define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */ 1756*91f16700Schasinglulu /* AP_MDSRC_REQ (0x10006000+0x430) */ 1757*91f16700Schasinglulu #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1758*91f16700Schasinglulu #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1759*91f16700Schasinglulu #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1760*91f16700Schasinglulu #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1761*91f16700Schasinglulu #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1762*91f16700Schasinglulu #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1763*91f16700Schasinglulu /* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */ 1764*91f16700Schasinglulu #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1765*91f16700Schasinglulu /* SPM2MD_DVFS_CON (0x10006000+0x438) */ 1766*91f16700Schasinglulu #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1767*91f16700Schasinglulu /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ 1768*91f16700Schasinglulu #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1769*91f16700Schasinglulu /* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */ 1770*91f16700Schasinglulu #define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */ 1771*91f16700Schasinglulu /* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */ 1772*91f16700Schasinglulu #define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */ 1773*91f16700Schasinglulu /* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */ 1774*91f16700Schasinglulu #define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */ 1775*91f16700Schasinglulu /* SPM_PLL_CON (0x10006000+0x44C) */ 1776*91f16700Schasinglulu #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1777*91f16700Schasinglulu #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1778*91f16700Schasinglulu #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1779*91f16700Schasinglulu #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1780*91f16700Schasinglulu #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1781*91f16700Schasinglulu #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1782*91f16700Schasinglulu #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1783*91f16700Schasinglulu #define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */ 1784*91f16700Schasinglulu #define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */ 1785*91f16700Schasinglulu #define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */ 1786*91f16700Schasinglulu /* CPU_DVFS_REQ (0x10006000+0x450) */ 1787*91f16700Schasinglulu #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ 1788*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */ 1789*91f16700Schasinglulu #define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */ 1790*91f16700Schasinglulu #define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */ 1791*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */ 1792*91f16700Schasinglulu #define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */ 1793*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */ 1794*91f16700Schasinglulu #define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */ 1795*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */ 1796*91f16700Schasinglulu #define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */ 1797*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */ 1798*91f16700Schasinglulu #define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */ 1799*91f16700Schasinglulu /* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */ 1800*91f16700Schasinglulu #define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */ 1801*91f16700Schasinglulu #define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */ 1802*91f16700Schasinglulu /* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */ 1803*91f16700Schasinglulu #define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */ 1804*91f16700Schasinglulu /* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */ 1805*91f16700Schasinglulu #define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */ 1806*91f16700Schasinglulu /* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */ 1807*91f16700Schasinglulu #define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */ 1808*91f16700Schasinglulu #define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */ 1809*91f16700Schasinglulu #define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */ 1810*91f16700Schasinglulu #define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */ 1811*91f16700Schasinglulu #define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */ 1812*91f16700Schasinglulu #define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */ 1813*91f16700Schasinglulu /* RELAY_DVFS_LEVEL (0x10006000+0x478) */ 1814*91f16700Schasinglulu #define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1815*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */ 1816*91f16700Schasinglulu #define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */ 1817*91f16700Schasinglulu #define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */ 1818*91f16700Schasinglulu #define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */ 1819*91f16700Schasinglulu #define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */ 1820*91f16700Schasinglulu #define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */ 1821*91f16700Schasinglulu #define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */ 1822*91f16700Schasinglulu #define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */ 1823*91f16700Schasinglulu #define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */ 1824*91f16700Schasinglulu #define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */ 1825*91f16700Schasinglulu #define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */ 1826*91f16700Schasinglulu #define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */ 1827*91f16700Schasinglulu #define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */ 1828*91f16700Schasinglulu #define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */ 1829*91f16700Schasinglulu #define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */ 1830*91f16700Schasinglulu #define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */ 1831*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */ 1832*91f16700Schasinglulu #define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */ 1833*91f16700Schasinglulu #define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */ 1834*91f16700Schasinglulu #define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */ 1835*91f16700Schasinglulu #define SW_DMYRD_EN_LSB (1U << 6) /* 2b */ 1836*91f16700Schasinglulu #define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */ 1837*91f16700Schasinglulu #define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */ 1838*91f16700Schasinglulu #define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */ 1839*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */ 1840*91f16700Schasinglulu #define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */ 1841*91f16700Schasinglulu #define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */ 1842*91f16700Schasinglulu #define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */ 1843*91f16700Schasinglulu #define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */ 1844*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */ 1845*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */ 1846*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */ 1847*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */ 1848*91f16700Schasinglulu #define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */ 1849*91f16700Schasinglulu #define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */ 1850*91f16700Schasinglulu #define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */ 1851*91f16700Schasinglulu #define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */ 1852*91f16700Schasinglulu #define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */ 1853*91f16700Schasinglulu #define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */ 1854*91f16700Schasinglulu #define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */ 1855*91f16700Schasinglulu #define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */ 1856*91f16700Schasinglulu #define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */ 1857*91f16700Schasinglulu #define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */ 1858*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */ 1859*91f16700Schasinglulu #define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */ 1860*91f16700Schasinglulu #define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */ 1861*91f16700Schasinglulu #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */ 1862*91f16700Schasinglulu #define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */ 1863*91f16700Schasinglulu #define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */ 1864*91f16700Schasinglulu #define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */ 1865*91f16700Schasinglulu #define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */ 1866*91f16700Schasinglulu #define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */ 1867*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */ 1868*91f16700Schasinglulu #define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */ 1869*91f16700Schasinglulu #define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */ 1870*91f16700Schasinglulu #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */ 1871*91f16700Schasinglulu #define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */ 1872*91f16700Schasinglulu #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */ 1873*91f16700Schasinglulu #define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */ 1874*91f16700Schasinglulu #define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */ 1875*91f16700Schasinglulu #define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */ 1876*91f16700Schasinglulu #define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */ 1877*91f16700Schasinglulu #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */ 1878*91f16700Schasinglulu #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */ 1879*91f16700Schasinglulu #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */ 1880*91f16700Schasinglulu #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */ 1881*91f16700Schasinglulu #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */ 1882*91f16700Schasinglulu #define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */ 1883*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */ 1884*91f16700Schasinglulu #define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */ 1885*91f16700Schasinglulu #define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */ 1886*91f16700Schasinglulu #define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */ 1887*91f16700Schasinglulu #define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */ 1888*91f16700Schasinglulu #define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */ 1889*91f16700Schasinglulu #define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */ 1890*91f16700Schasinglulu #define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */ 1891*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */ 1892*91f16700Schasinglulu #define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */ 1893*91f16700Schasinglulu #define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */ 1894*91f16700Schasinglulu #define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */ 1895*91f16700Schasinglulu #define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */ 1896*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */ 1897*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */ 1898*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */ 1899*91f16700Schasinglulu #define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */ 1900*91f16700Schasinglulu #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */ 1901*91f16700Schasinglulu #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */ 1902*91f16700Schasinglulu #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */ 1903*91f16700Schasinglulu #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */ 1904*91f16700Schasinglulu #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */ 1905*91f16700Schasinglulu #define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */ 1906*91f16700Schasinglulu #define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */ 1907*91f16700Schasinglulu #define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */ 1908*91f16700Schasinglulu #define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */ 1909*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */ 1910*91f16700Schasinglulu #define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */ 1911*91f16700Schasinglulu #define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */ 1912*91f16700Schasinglulu #define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */ 1913*91f16700Schasinglulu #define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */ 1914*91f16700Schasinglulu #define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */ 1915*91f16700Schasinglulu #define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */ 1916*91f16700Schasinglulu #define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */ 1917*91f16700Schasinglulu #define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */ 1918*91f16700Schasinglulu /* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */ 1919*91f16700Schasinglulu #define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */ 1920*91f16700Schasinglulu #define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */ 1921*91f16700Schasinglulu #define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */ 1922*91f16700Schasinglulu #define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */ 1923*91f16700Schasinglulu #define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */ 1924*91f16700Schasinglulu #define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */ 1925*91f16700Schasinglulu #define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */ 1926*91f16700Schasinglulu #define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */ 1927*91f16700Schasinglulu #define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */ 1928*91f16700Schasinglulu #define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */ 1929*91f16700Schasinglulu #define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */ 1930*91f16700Schasinglulu #define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */ 1931*91f16700Schasinglulu #define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */ 1932*91f16700Schasinglulu #define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */ 1933*91f16700Schasinglulu #define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */ 1934*91f16700Schasinglulu #define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */ 1935*91f16700Schasinglulu #define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */ 1936*91f16700Schasinglulu #define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */ 1937*91f16700Schasinglulu #define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */ 1938*91f16700Schasinglulu #define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */ 1939*91f16700Schasinglulu #define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */ 1940*91f16700Schasinglulu #define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */ 1941*91f16700Schasinglulu /* SPM_DVFS_LEVEL (0x10006000+0x4A4) */ 1942*91f16700Schasinglulu #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 1943*91f16700Schasinglulu /* SPM_CIRQ_CON (0x10006000+0x4A8) */ 1944*91f16700Schasinglulu #define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */ 1945*91f16700Schasinglulu /* SPM_DVFS_MISC (0x10006000+0x4AC) */ 1946*91f16700Schasinglulu #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 1947*91f16700Schasinglulu #define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */ 1948*91f16700Schasinglulu #define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ 1949*91f16700Schasinglulu #define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */ 1950*91f16700Schasinglulu #define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ 1951*91f16700Schasinglulu #define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */ 1952*91f16700Schasinglulu #define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */ 1953*91f16700Schasinglulu #define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */ 1954*91f16700Schasinglulu #define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */ 1955*91f16700Schasinglulu #define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */ 1956*91f16700Schasinglulu /* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */ 1957*91f16700Schasinglulu #define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */ 1958*91f16700Schasinglulu #define VS1_INIT_LSB (1U << 2) /* 1b */ 1959*91f16700Schasinglulu #define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */ 1960*91f16700Schasinglulu #define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */ 1961*91f16700Schasinglulu #define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */ 1962*91f16700Schasinglulu #define VS1_TRIGGER_LSB (1U << 9) /* 1b */ 1963*91f16700Schasinglulu #define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */ 1964*91f16700Schasinglulu #define VS2_INIT_LSB (1U << 13) /* 1b */ 1965*91f16700Schasinglulu #define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */ 1966*91f16700Schasinglulu #define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */ 1967*91f16700Schasinglulu #define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */ 1968*91f16700Schasinglulu #define VS2_TRIGGER_LSB (1U << 23) /* 1b */ 1969*91f16700Schasinglulu #define VS1_FORCE_LSB (1U << 24) /* 1b */ 1970*91f16700Schasinglulu #define VS2_FORCE_LSB (1U << 25) /* 1b */ 1971*91f16700Schasinglulu #define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */ 1972*91f16700Schasinglulu #define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */ 1973*91f16700Schasinglulu /* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */ 1974*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1975*91f16700Schasinglulu /* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */ 1976*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1977*91f16700Schasinglulu /* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */ 1978*91f16700Schasinglulu #define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1979*91f16700Schasinglulu /* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */ 1980*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1981*91f16700Schasinglulu /* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */ 1982*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1983*91f16700Schasinglulu /* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */ 1984*91f16700Schasinglulu #define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1985*91f16700Schasinglulu /* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */ 1986*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1987*91f16700Schasinglulu /* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */ 1988*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1989*91f16700Schasinglulu /* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */ 1990*91f16700Schasinglulu #define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1991*91f16700Schasinglulu /* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */ 1992*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1993*91f16700Schasinglulu /* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */ 1994*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */ 1995*91f16700Schasinglulu /* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */ 1996*91f16700Schasinglulu #define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */ 1997*91f16700Schasinglulu /* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */ 1998*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */ 1999*91f16700Schasinglulu /* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */ 2000*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */ 2001*91f16700Schasinglulu /* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */ 2002*91f16700Schasinglulu #define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */ 2003*91f16700Schasinglulu /* SPM_CG_CHECK_CON (0x10006000+0x4F0) */ 2004*91f16700Schasinglulu #define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */ 2005*91f16700Schasinglulu #define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */ 2006*91f16700Schasinglulu #define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */ 2007*91f16700Schasinglulu #define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */ 2008*91f16700Schasinglulu #define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */ 2009*91f16700Schasinglulu #define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */ 2010*91f16700Schasinglulu #define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */ 2011*91f16700Schasinglulu #define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */ 2012*91f16700Schasinglulu #define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */ 2013*91f16700Schasinglulu /* SPM_SRC_RDY_STA (0x10006000+0x4F4) */ 2014*91f16700Schasinglulu #define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */ 2015*91f16700Schasinglulu #define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */ 2016*91f16700Schasinglulu /* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */ 2017*91f16700Schasinglulu #define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */ 2018*91f16700Schasinglulu #define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */ 2019*91f16700Schasinglulu /* SPM_FORCE_DVFS (0x10006000+0x4FC) */ 2020*91f16700Schasinglulu #define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */ 2021*91f16700Schasinglulu /* SRCLKEN_RC_CFG (0x10006000+0x500) */ 2022*91f16700Schasinglulu #define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */ 2023*91f16700Schasinglulu /* RC_CENTRAL_CFG1 (0x10006000+0x504) */ 2024*91f16700Schasinglulu #define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */ 2025*91f16700Schasinglulu /* RC_CENTRAL_CFG2 (0x10006000+0x508) */ 2026*91f16700Schasinglulu #define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */ 2027*91f16700Schasinglulu /* RC_CMD_ARB_CFG (0x10006000+0x50C) */ 2028*91f16700Schasinglulu #define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */ 2029*91f16700Schasinglulu /* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */ 2030*91f16700Schasinglulu #define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */ 2031*91f16700Schasinglulu #define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */ 2032*91f16700Schasinglulu /* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */ 2033*91f16700Schasinglulu #define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */ 2034*91f16700Schasinglulu #define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */ 2035*91f16700Schasinglulu /* RC_DCXO_FPM_CFG (0x10006000+0x518) */ 2036*91f16700Schasinglulu #define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */ 2037*91f16700Schasinglulu /* RC_CENTRAL_CFG3 (0x10006000+0x51C) */ 2038*91f16700Schasinglulu #define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */ 2039*91f16700Schasinglulu /* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */ 2040*91f16700Schasinglulu #define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2041*91f16700Schasinglulu #define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */ 2042*91f16700Schasinglulu #define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */ 2043*91f16700Schasinglulu /* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */ 2044*91f16700Schasinglulu #define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2045*91f16700Schasinglulu /* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */ 2046*91f16700Schasinglulu #define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2047*91f16700Schasinglulu /* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */ 2048*91f16700Schasinglulu #define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2049*91f16700Schasinglulu /* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */ 2050*91f16700Schasinglulu #define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2051*91f16700Schasinglulu /* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */ 2052*91f16700Schasinglulu #define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2053*91f16700Schasinglulu /* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */ 2054*91f16700Schasinglulu #define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2055*91f16700Schasinglulu /* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */ 2056*91f16700Schasinglulu #define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2057*91f16700Schasinglulu /* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */ 2058*91f16700Schasinglulu #define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2059*91f16700Schasinglulu /* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */ 2060*91f16700Schasinglulu #define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2061*91f16700Schasinglulu /* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */ 2062*91f16700Schasinglulu #define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2063*91f16700Schasinglulu /* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */ 2064*91f16700Schasinglulu #define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2065*91f16700Schasinglulu /* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */ 2066*91f16700Schasinglulu #define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */ 2067*91f16700Schasinglulu /* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */ 2068*91f16700Schasinglulu #define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */ 2069*91f16700Schasinglulu /* RC_CENTRAL_CFG4 (0x10006000+0x558) */ 2070*91f16700Schasinglulu #define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */ 2071*91f16700Schasinglulu /* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */ 2072*91f16700Schasinglulu #define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */ 2073*91f16700Schasinglulu /* RC_DEBUG_CFG (0x10006000+0x564) */ 2074*91f16700Schasinglulu #define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */ 2075*91f16700Schasinglulu /* RC_MISC_0 (0x10006000+0x5B4) */ 2076*91f16700Schasinglulu #define SRCCLKENO_LSB (1U << 0) /* 2b */ 2077*91f16700Schasinglulu #define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */ 2078*91f16700Schasinglulu #define RC_VREQ_LSB (1U << 5) /* 1b */ 2079*91f16700Schasinglulu #define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */ 2080*91f16700Schasinglulu /* RC_SPM_CTRL (0x10006000+0x448) */ 2081*91f16700Schasinglulu #define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */ 2082*91f16700Schasinglulu #define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */ 2083*91f16700Schasinglulu #define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */ 2084*91f16700Schasinglulu /* SUBSYS_INTF_CFG (0x10006000+0x5BC) */ 2085*91f16700Schasinglulu #define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */ 2086*91f16700Schasinglulu #define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */ 2087*91f16700Schasinglulu /* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */ 2088*91f16700Schasinglulu #define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */ 2089*91f16700Schasinglulu /* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */ 2090*91f16700Schasinglulu #define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */ 2091*91f16700Schasinglulu /* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */ 2092*91f16700Schasinglulu #define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */ 2093*91f16700Schasinglulu /* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */ 2094*91f16700Schasinglulu #define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */ 2095*91f16700Schasinglulu /* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */ 2096*91f16700Schasinglulu #define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */ 2097*91f16700Schasinglulu /* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */ 2098*91f16700Schasinglulu #define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */ 2099*91f16700Schasinglulu /* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */ 2100*91f16700Schasinglulu #define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */ 2101*91f16700Schasinglulu /* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */ 2102*91f16700Schasinglulu #define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */ 2103*91f16700Schasinglulu /* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */ 2104*91f16700Schasinglulu #define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */ 2105*91f16700Schasinglulu /* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */ 2106*91f16700Schasinglulu #define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */ 2107*91f16700Schasinglulu /* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */ 2108*91f16700Schasinglulu #define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */ 2109*91f16700Schasinglulu /* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */ 2110*91f16700Schasinglulu #define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */ 2111*91f16700Schasinglulu /* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */ 2112*91f16700Schasinglulu #define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */ 2113*91f16700Schasinglulu /* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */ 2114*91f16700Schasinglulu #define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */ 2115*91f16700Schasinglulu /* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */ 2116*91f16700Schasinglulu #define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */ 2117*91f16700Schasinglulu /* SPM_SW_FLAG_0 (0x10006000+0x600) */ 2118*91f16700Schasinglulu #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 2119*91f16700Schasinglulu /* SPM_SW_DEBUG_0 (0x10006000+0x604) */ 2120*91f16700Schasinglulu #define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */ 2121*91f16700Schasinglulu /* SPM_SW_FLAG_1 (0x10006000+0x608) */ 2122*91f16700Schasinglulu #define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */ 2123*91f16700Schasinglulu /* SPM_SW_DEBUG_1 (0x10006000+0x60C) */ 2124*91f16700Schasinglulu #define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */ 2125*91f16700Schasinglulu /* SPM_SW_RSV_0 (0x10006000+0x610) */ 2126*91f16700Schasinglulu #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 2127*91f16700Schasinglulu /* SPM_SW_RSV_1 (0x10006000+0x614) */ 2128*91f16700Schasinglulu #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 2129*91f16700Schasinglulu /* SPM_SW_RSV_2 (0x10006000+0x618) */ 2130*91f16700Schasinglulu #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 2131*91f16700Schasinglulu /* SPM_SW_RSV_3 (0x10006000+0x61C) */ 2132*91f16700Schasinglulu #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 2133*91f16700Schasinglulu /* SPM_SW_RSV_4 (0x10006000+0x620) */ 2134*91f16700Schasinglulu #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 2135*91f16700Schasinglulu /* SPM_SW_RSV_5 (0x10006000+0x624) */ 2136*91f16700Schasinglulu #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 2137*91f16700Schasinglulu /* SPM_SW_RSV_6 (0x10006000+0x628) */ 2138*91f16700Schasinglulu #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 2139*91f16700Schasinglulu /* SPM_SW_RSV_7 (0x10006000+0x62C) */ 2140*91f16700Schasinglulu #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 2141*91f16700Schasinglulu /* SPM_SW_RSV_8 (0x10006000+0x630) */ 2142*91f16700Schasinglulu #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 2143*91f16700Schasinglulu /* SPM_BK_WAKE_EVENT (0x10006000+0x634) */ 2144*91f16700Schasinglulu #define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */ 2145*91f16700Schasinglulu /* SPM_BK_VTCXO_DUR (0x10006000+0x638) */ 2146*91f16700Schasinglulu #define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */ 2147*91f16700Schasinglulu /* SPM_BK_WAKE_MISC (0x10006000+0x63C) */ 2148*91f16700Schasinglulu #define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */ 2149*91f16700Schasinglulu /* SPM_BK_PCM_TIMER (0x10006000+0x640) */ 2150*91f16700Schasinglulu #define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */ 2151*91f16700Schasinglulu /* SPM_RSV_CON_0 (0x10006000+0x650) */ 2152*91f16700Schasinglulu #define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */ 2153*91f16700Schasinglulu /* SPM_RSV_CON_1 (0x10006000+0x654) */ 2154*91f16700Schasinglulu #define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */ 2155*91f16700Schasinglulu /* SPM_RSV_STA_0 (0x10006000+0x658) */ 2156*91f16700Schasinglulu #define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */ 2157*91f16700Schasinglulu /* SPM_RSV_STA_1 (0x10006000+0x65C) */ 2158*91f16700Schasinglulu #define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */ 2159*91f16700Schasinglulu /* SPM_SPARE_CON (0x10006000+0x660) */ 2160*91f16700Schasinglulu #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 2161*91f16700Schasinglulu /* SPM_SPARE_CON_SET (0x10006000+0x664) */ 2162*91f16700Schasinglulu #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 2163*91f16700Schasinglulu /* SPM_SPARE_CON_CLR (0x10006000+0x668) */ 2164*91f16700Schasinglulu #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 2165*91f16700Schasinglulu /* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */ 2166*91f16700Schasinglulu #define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */ 2167*91f16700Schasinglulu #define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */ 2168*91f16700Schasinglulu /* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */ 2169*91f16700Schasinglulu #define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */ 2170*91f16700Schasinglulu #define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */ 2171*91f16700Schasinglulu /* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */ 2172*91f16700Schasinglulu #define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */ 2173*91f16700Schasinglulu #define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */ 2174*91f16700Schasinglulu /* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */ 2175*91f16700Schasinglulu #define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */ 2176*91f16700Schasinglulu #define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */ 2177*91f16700Schasinglulu /* SCP_VCORE_LEVEL (0x10006000+0x67C) */ 2178*91f16700Schasinglulu #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */ 2179*91f16700Schasinglulu /* SC_MM_CK_SEL_CON (0x10006000+0x680) */ 2180*91f16700Schasinglulu #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 2181*91f16700Schasinglulu #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 2182*91f16700Schasinglulu /* SPARE_ACK_MASK (0x10006000+0x684) */ 2183*91f16700Schasinglulu #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 2184*91f16700Schasinglulu /* SPM_DV_CON_0 (0x10006000+0x68C) */ 2185*91f16700Schasinglulu #define SPM_DV_CON_0_LSB (1U << 0) /* 32b */ 2186*91f16700Schasinglulu /* SPM_DV_CON_1 (0x10006000+0x690) */ 2187*91f16700Schasinglulu #define SPM_DV_CON_1_LSB (1U << 0) /* 32b */ 2188*91f16700Schasinglulu /* SPM_DV_STA (0x10006000+0x694) */ 2189*91f16700Schasinglulu #define SPM_DV_STA_LSB (1U << 0) /* 32b */ 2190*91f16700Schasinglulu /* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */ 2191*91f16700Schasinglulu #define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */ 2192*91f16700Schasinglulu /* SPM_SEMA_M0 (0x10006000+0x69C) */ 2193*91f16700Schasinglulu #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 2194*91f16700Schasinglulu /* SPM_SEMA_M1 (0x10006000+0x6A0) */ 2195*91f16700Schasinglulu #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 2196*91f16700Schasinglulu /* SPM_SEMA_M2 (0x10006000+0x6A4) */ 2197*91f16700Schasinglulu #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 2198*91f16700Schasinglulu /* SPM_SEMA_M3 (0x10006000+0x6A8) */ 2199*91f16700Schasinglulu #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 2200*91f16700Schasinglulu /* SPM_SEMA_M4 (0x10006000+0x6AC) */ 2201*91f16700Schasinglulu #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 2202*91f16700Schasinglulu /* SPM_SEMA_M5 (0x10006000+0x6B0) */ 2203*91f16700Schasinglulu #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 2204*91f16700Schasinglulu /* SPM_SEMA_M6 (0x10006000+0x6B4) */ 2205*91f16700Schasinglulu #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 2206*91f16700Schasinglulu /* SPM_SEMA_M7 (0x10006000+0x6B8) */ 2207*91f16700Schasinglulu #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 2208*91f16700Schasinglulu /* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */ 2209*91f16700Schasinglulu #define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */ 2210*91f16700Schasinglulu /* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */ 2211*91f16700Schasinglulu #define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */ 2212*91f16700Schasinglulu /* SPM_ADSP_IRQ (0x10006000+0x6C4) */ 2213*91f16700Schasinglulu #define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */ 2214*91f16700Schasinglulu #define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */ 2215*91f16700Schasinglulu /* SPM_MD32_IRQ (0x10006000+0x6C8) */ 2216*91f16700Schasinglulu #define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */ 2217*91f16700Schasinglulu #define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */ 2218*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */ 2219*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 2220*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */ 2221*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 2222*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */ 2223*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 2224*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */ 2225*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 2226*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */ 2227*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 2228*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */ 2229*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 2230*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */ 2231*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 2232*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */ 2233*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 2234*91f16700Schasinglulu /* UFS_PSRI_SW (0x10006000+0x6EC) */ 2235*91f16700Schasinglulu #define UFS_PSRI_SW_LSB (1U << 0) /* 1b */ 2236*91f16700Schasinglulu /* UFS_PSRI_SW_SET (0x10006000+0x6F0) */ 2237*91f16700Schasinglulu #define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */ 2238*91f16700Schasinglulu /* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */ 2239*91f16700Schasinglulu #define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */ 2240*91f16700Schasinglulu /* SPM_AP_SEMA (0x10006000+0x6F8) */ 2241*91f16700Schasinglulu #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 2242*91f16700Schasinglulu /* SPM_SPM_SEMA (0x10006000+0x6FC) */ 2243*91f16700Schasinglulu #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 2244*91f16700Schasinglulu /* SPM_DVFS_CON (0x10006000+0x700) */ 2245*91f16700Schasinglulu #define SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 2246*91f16700Schasinglulu /* SPM_DVFS_CON_STA (0x10006000+0x704) */ 2247*91f16700Schasinglulu #define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */ 2248*91f16700Schasinglulu /* SPM_PMIC_SPMI_CON (0x10006000+0x708) */ 2249*91f16700Schasinglulu #define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */ 2250*91f16700Schasinglulu #define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */ 2251*91f16700Schasinglulu #define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */ 2252*91f16700Schasinglulu #define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */ 2253*91f16700Schasinglulu /* SPM_DVFS_CMD0 (0x10006000+0x710) */ 2254*91f16700Schasinglulu #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 2255*91f16700Schasinglulu /* SPM_DVFS_CMD1 (0x10006000+0x714) */ 2256*91f16700Schasinglulu #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 2257*91f16700Schasinglulu /* SPM_DVFS_CMD2 (0x10006000+0x718) */ 2258*91f16700Schasinglulu #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 2259*91f16700Schasinglulu /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ 2260*91f16700Schasinglulu #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 2261*91f16700Schasinglulu /* SPM_DVFS_CMD4 (0x10006000+0x720) */ 2262*91f16700Schasinglulu #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 2263*91f16700Schasinglulu /* SPM_DVFS_CMD5 (0x10006000+0x724) */ 2264*91f16700Schasinglulu #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 2265*91f16700Schasinglulu /* SPM_DVFS_CMD6 (0x10006000+0x728) */ 2266*91f16700Schasinglulu #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 2267*91f16700Schasinglulu /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ 2268*91f16700Schasinglulu #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 2269*91f16700Schasinglulu /* SPM_DVFS_CMD8 (0x10006000+0x730) */ 2270*91f16700Schasinglulu #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 2271*91f16700Schasinglulu /* SPM_DVFS_CMD9 (0x10006000+0x734) */ 2272*91f16700Schasinglulu #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 2273*91f16700Schasinglulu /* SPM_DVFS_CMD10 (0x10006000+0x738) */ 2274*91f16700Schasinglulu #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 2275*91f16700Schasinglulu /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ 2276*91f16700Schasinglulu #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 2277*91f16700Schasinglulu /* SPM_DVFS_CMD12 (0x10006000+0x740) */ 2278*91f16700Schasinglulu #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 2279*91f16700Schasinglulu /* SPM_DVFS_CMD13 (0x10006000+0x744) */ 2280*91f16700Schasinglulu #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 2281*91f16700Schasinglulu /* SPM_DVFS_CMD14 (0x10006000+0x748) */ 2282*91f16700Schasinglulu #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 2283*91f16700Schasinglulu /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ 2284*91f16700Schasinglulu #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 2285*91f16700Schasinglulu /* SPM_DVFS_CMD16 (0x10006000+0x750) */ 2286*91f16700Schasinglulu #define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */ 2287*91f16700Schasinglulu /* SPM_DVFS_CMD17 (0x10006000+0x754) */ 2288*91f16700Schasinglulu #define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */ 2289*91f16700Schasinglulu /* SPM_DVFS_CMD18 (0x10006000+0x758) */ 2290*91f16700Schasinglulu #define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */ 2291*91f16700Schasinglulu /* SPM_DVFS_CMD19 (0x10006000+0x75C) */ 2292*91f16700Schasinglulu #define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */ 2293*91f16700Schasinglulu /* SPM_DVFS_CMD20 (0x10006000+0x760) */ 2294*91f16700Schasinglulu #define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */ 2295*91f16700Schasinglulu /* SPM_DVFS_CMD21 (0x10006000+0x764) */ 2296*91f16700Schasinglulu #define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */ 2297*91f16700Schasinglulu /* SPM_DVFS_CMD22 (0x10006000+0x768) */ 2298*91f16700Schasinglulu #define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */ 2299*91f16700Schasinglulu /* SPM_DVFS_CMD23 (0x10006000+0x76C) */ 2300*91f16700Schasinglulu #define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */ 2301*91f16700Schasinglulu /* SYS_TIMER_VALUE_L (0x10006000+0x770) */ 2302*91f16700Schasinglulu #define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */ 2303*91f16700Schasinglulu /* SYS_TIMER_VALUE_H (0x10006000+0x774) */ 2304*91f16700Schasinglulu #define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */ 2305*91f16700Schasinglulu /* SYS_TIMER_START_L (0x10006000+0x778) */ 2306*91f16700Schasinglulu #define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */ 2307*91f16700Schasinglulu /* SYS_TIMER_START_H (0x10006000+0x77C) */ 2308*91f16700Schasinglulu #define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */ 2309*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */ 2310*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2311*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */ 2312*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2313*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */ 2314*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2315*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */ 2316*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2317*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */ 2318*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2319*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */ 2320*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2321*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */ 2322*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2323*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */ 2324*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2325*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */ 2326*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2327*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */ 2328*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2329*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */ 2330*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2331*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */ 2332*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2333*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */ 2334*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2335*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */ 2336*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2337*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */ 2338*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2339*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */ 2340*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2341*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */ 2342*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */ 2343*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */ 2344*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */ 2345*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */ 2346*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */ 2347*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */ 2348*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */ 2349*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */ 2350*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */ 2351*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */ 2352*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */ 2353*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */ 2354*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */ 2355*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */ 2356*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */ 2357*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */ 2358*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */ 2359*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */ 2360*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */ 2361*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */ 2362*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */ 2363*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */ 2364*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */ 2365*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */ 2366*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */ 2367*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */ 2368*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */ 2369*91f16700Schasinglulu /* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */ 2370*91f16700Schasinglulu #define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */ 2371*91f16700Schasinglulu /* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */ 2372*91f16700Schasinglulu #define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */ 2373*91f16700Schasinglulu /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ 2374*91f16700Schasinglulu #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 2375*91f16700Schasinglulu /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ 2376*91f16700Schasinglulu #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 2377*91f16700Schasinglulu /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ 2378*91f16700Schasinglulu #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 2379*91f16700Schasinglulu /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ 2380*91f16700Schasinglulu #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 2381*91f16700Schasinglulu /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ 2382*91f16700Schasinglulu #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 2383*91f16700Schasinglulu /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ 2384*91f16700Schasinglulu #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 2385*91f16700Schasinglulu /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ 2386*91f16700Schasinglulu #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 2387*91f16700Schasinglulu /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ 2388*91f16700Schasinglulu #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 2389*91f16700Schasinglulu /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ 2390*91f16700Schasinglulu #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 2391*91f16700Schasinglulu /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ 2392*91f16700Schasinglulu #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 2393*91f16700Schasinglulu /* PCM_WDT_LATCH_10 (0x10006000+0x828) */ 2394*91f16700Schasinglulu #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 2395*91f16700Schasinglulu /* PCM_WDT_LATCH_11 (0x10006000+0x82C) */ 2396*91f16700Schasinglulu #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 2397*91f16700Schasinglulu /* PCM_WDT_LATCH_12 (0x10006000+0x830) */ 2398*91f16700Schasinglulu #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 2399*91f16700Schasinglulu /* PCM_WDT_LATCH_13 (0x10006000+0x834) */ 2400*91f16700Schasinglulu #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 2401*91f16700Schasinglulu /* PCM_WDT_LATCH_14 (0x10006000+0x838) */ 2402*91f16700Schasinglulu #define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */ 2403*91f16700Schasinglulu /* PCM_WDT_LATCH_15 (0x10006000+0x83C) */ 2404*91f16700Schasinglulu #define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */ 2405*91f16700Schasinglulu /* PCM_WDT_LATCH_16 (0x10006000+0x840) */ 2406*91f16700Schasinglulu #define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */ 2407*91f16700Schasinglulu /* PCM_WDT_LATCH_17 (0x10006000+0x844) */ 2408*91f16700Schasinglulu #define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */ 2409*91f16700Schasinglulu /* PCM_WDT_LATCH_18 (0x10006000+0x848) */ 2410*91f16700Schasinglulu #define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */ 2411*91f16700Schasinglulu /* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */ 2412*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2413*91f16700Schasinglulu /* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */ 2414*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */ 2415*91f16700Schasinglulu /* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */ 2416*91f16700Schasinglulu #define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */ 2417*91f16700Schasinglulu /* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */ 2418*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */ 2419*91f16700Schasinglulu /* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */ 2420*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */ 2421*91f16700Schasinglulu /* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */ 2422*91f16700Schasinglulu #define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */ 2423*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */ 2424*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */ 2425*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */ 2426*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */ 2427*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */ 2428*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */ 2429*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */ 2430*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */ 2431*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */ 2432*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */ 2433*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */ 2434*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */ 2435*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */ 2436*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */ 2437*91f16700Schasinglulu /* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */ 2438*91f16700Schasinglulu #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */ 2439*91f16700Schasinglulu /* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */ 2440*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */ 2441*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */ 2442*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */ 2443*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */ 2444*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */ 2445*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */ 2446*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */ 2447*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */ 2448*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */ 2449*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */ 2450*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */ 2451*91f16700Schasinglulu /* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */ 2452*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */ 2453*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */ 2454*91f16700Schasinglulu /* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */ 2455*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */ 2456*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */ 2457*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */ 2458*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */ 2459*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */ 2460*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */ 2461*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */ 2462*91f16700Schasinglulu /* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */ 2463*91f16700Schasinglulu #define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */ 2464*91f16700Schasinglulu /* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */ 2465*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */ 2466*91f16700Schasinglulu /* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */ 2467*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */ 2468*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */ 2469*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */ 2470*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */ 2471*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */ 2472*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */ 2473*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */ 2474*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */ 2475*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */ 2476*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */ 2477*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */ 2478*91f16700Schasinglulu /* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */ 2479*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */ 2480*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */ 2481*91f16700Schasinglulu /* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */ 2482*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */ 2483*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */ 2484*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */ 2485*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */ 2486*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */ 2487*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */ 2488*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */ 2489*91f16700Schasinglulu /* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */ 2490*91f16700Schasinglulu #define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */ 2491*91f16700Schasinglulu /* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */ 2492*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */ 2493*91f16700Schasinglulu /* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */ 2494*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */ 2495*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */ 2496*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */ 2497*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */ 2498*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */ 2499*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */ 2500*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */ 2501*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */ 2502*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */ 2503*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */ 2504*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */ 2505*91f16700Schasinglulu /* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */ 2506*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */ 2507*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */ 2508*91f16700Schasinglulu /* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */ 2509*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */ 2510*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */ 2511*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */ 2512*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */ 2513*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */ 2514*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */ 2515*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */ 2516*91f16700Schasinglulu /* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */ 2517*91f16700Schasinglulu #define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */ 2518*91f16700Schasinglulu /* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */ 2519*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */ 2520*91f16700Schasinglulu /* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */ 2521*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */ 2522*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */ 2523*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */ 2524*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */ 2525*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */ 2526*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */ 2527*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */ 2528*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */ 2529*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */ 2530*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */ 2531*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */ 2532*91f16700Schasinglulu /* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */ 2533*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */ 2534*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */ 2535*91f16700Schasinglulu /* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */ 2536*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */ 2537*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */ 2538*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */ 2539*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */ 2540*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */ 2541*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */ 2542*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */ 2543*91f16700Schasinglulu /* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */ 2544*91f16700Schasinglulu #define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */ 2545*91f16700Schasinglulu /* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */ 2546*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */ 2547*91f16700Schasinglulu /* SPM_COUNTER_0 (0x10006000+0x978) */ 2548*91f16700Schasinglulu #define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */ 2549*91f16700Schasinglulu #define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */ 2550*91f16700Schasinglulu #define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */ 2551*91f16700Schasinglulu #define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */ 2552*91f16700Schasinglulu #define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */ 2553*91f16700Schasinglulu #define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */ 2554*91f16700Schasinglulu /* SPM_COUNTER_1 (0x10006000+0x97C) */ 2555*91f16700Schasinglulu #define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */ 2556*91f16700Schasinglulu #define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */ 2557*91f16700Schasinglulu #define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */ 2558*91f16700Schasinglulu #define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */ 2559*91f16700Schasinglulu #define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */ 2560*91f16700Schasinglulu #define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */ 2561*91f16700Schasinglulu /* SPM_COUNTER_2 (0x10006000+0x980) */ 2562*91f16700Schasinglulu #define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */ 2563*91f16700Schasinglulu #define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */ 2564*91f16700Schasinglulu #define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */ 2565*91f16700Schasinglulu #define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */ 2566*91f16700Schasinglulu #define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */ 2567*91f16700Schasinglulu #define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */ 2568*91f16700Schasinglulu /* SYS_TIMER_CON (0x10006000+0x98C) */ 2569*91f16700Schasinglulu #define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ 2570*91f16700Schasinglulu #define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */ 2571*91f16700Schasinglulu #define SYS_TIMER_ID_LSB (1U << 8) /* 8b */ 2572*91f16700Schasinglulu #define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */ 2573*91f16700Schasinglulu /* RC_FSM_STA_0 (0x10006000+0xE00) */ 2574*91f16700Schasinglulu #define RC_FSM_STA_0_LSB (1U << 0) /* 32b */ 2575*91f16700Schasinglulu /* RC_CMD_STA_0 (0x10006000+0xE04) */ 2576*91f16700Schasinglulu #define RC_CMD_STA_0_LSB (1U << 0) /* 32b */ 2577*91f16700Schasinglulu /* RC_CMD_STA_1 (0x10006000+0xE08) */ 2578*91f16700Schasinglulu #define RC_CMD_STA_1_LSB (1U << 0) /* 32b */ 2579*91f16700Schasinglulu /* RC_SPI_STA_0 (0x10006000+0xE0C) */ 2580*91f16700Schasinglulu #define RC_SPI_STA_0_LSB (1U << 0) /* 32b */ 2581*91f16700Schasinglulu /* RC_PI_PO_STA_0 (0x10006000+0xE10) */ 2582*91f16700Schasinglulu #define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */ 2583*91f16700Schasinglulu /* RC_M00_REQ_STA_0 (0x10006000+0xE14) */ 2584*91f16700Schasinglulu #define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */ 2585*91f16700Schasinglulu /* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */ 2586*91f16700Schasinglulu #define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */ 2587*91f16700Schasinglulu /* RC_M02_REQ_STA_0 (0x10006000+0xE20) */ 2588*91f16700Schasinglulu #define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */ 2589*91f16700Schasinglulu /* RC_M03_REQ_STA_0 (0x10006000+0xE24) */ 2590*91f16700Schasinglulu #define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */ 2591*91f16700Schasinglulu /* RC_M04_REQ_STA_0 (0x10006000+0xE28) */ 2592*91f16700Schasinglulu #define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */ 2593*91f16700Schasinglulu /* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */ 2594*91f16700Schasinglulu #define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */ 2595*91f16700Schasinglulu /* RC_M06_REQ_STA_0 (0x10006000+0xE30) */ 2596*91f16700Schasinglulu #define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */ 2597*91f16700Schasinglulu /* RC_M07_REQ_STA_0 (0x10006000+0xE34) */ 2598*91f16700Schasinglulu #define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */ 2599*91f16700Schasinglulu /* RC_M08_REQ_STA_0 (0x10006000+0xE38) */ 2600*91f16700Schasinglulu #define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */ 2601*91f16700Schasinglulu /* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */ 2602*91f16700Schasinglulu #define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */ 2603*91f16700Schasinglulu /* RC_M10_REQ_STA_0 (0x10006000+0xE40) */ 2604*91f16700Schasinglulu #define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */ 2605*91f16700Schasinglulu /* RC_M11_REQ_STA_0 (0x10006000+0xE44) */ 2606*91f16700Schasinglulu #define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */ 2607*91f16700Schasinglulu /* RC_M12_REQ_STA_0 (0x10006000+0xE48) */ 2608*91f16700Schasinglulu #define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */ 2609*91f16700Schasinglulu /* RC_DEBUG_STA_0 (0x10006000+0xE4C) */ 2610*91f16700Schasinglulu #define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */ 2611*91f16700Schasinglulu /* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */ 2612*91f16700Schasinglulu #define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */ 2613*91f16700Schasinglulu /* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */ 2614*91f16700Schasinglulu #define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */ 2615*91f16700Schasinglulu /* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */ 2616*91f16700Schasinglulu #define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */ 2617*91f16700Schasinglulu /* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */ 2618*91f16700Schasinglulu #define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */ 2619*91f16700Schasinglulu /* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */ 2620*91f16700Schasinglulu #define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */ 2621*91f16700Schasinglulu /* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */ 2622*91f16700Schasinglulu #define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */ 2623*91f16700Schasinglulu /* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */ 2624*91f16700Schasinglulu #define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */ 2625*91f16700Schasinglulu /* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */ 2626*91f16700Schasinglulu #define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */ 2627*91f16700Schasinglulu /* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */ 2628*91f16700Schasinglulu #define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */ 2629*91f16700Schasinglulu /* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */ 2630*91f16700Schasinglulu #define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */ 2631*91f16700Schasinglulu /* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */ 2632*91f16700Schasinglulu #define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */ 2633*91f16700Schasinglulu /* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */ 2634*91f16700Schasinglulu #define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */ 2635*91f16700Schasinglulu /* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */ 2636*91f16700Schasinglulu #define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */ 2637*91f16700Schasinglulu /* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */ 2638*91f16700Schasinglulu #define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */ 2639*91f16700Schasinglulu /* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */ 2640*91f16700Schasinglulu #define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */ 2641*91f16700Schasinglulu /* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */ 2642*91f16700Schasinglulu #define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */ 2643*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */ 2644*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */ 2645*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */ 2646*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */ 2647*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */ 2648*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */ 2649*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */ 2650*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */ 2651*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */ 2652*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */ 2653*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */ 2654*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */ 2655*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */ 2656*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */ 2657*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */ 2658*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */ 2659*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */ 2660*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */ 2661*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */ 2662*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */ 2663*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */ 2664*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */ 2665*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */ 2666*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */ 2667*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */ 2668*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */ 2669*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */ 2670*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */ 2671*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */ 2672*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */ 2673*91f16700Schasinglulu /* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */ 2674*91f16700Schasinglulu #define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */ 2675*91f16700Schasinglulu /* PCM_WDT_LATCH_19 (0x10006000+0xED8) */ 2676*91f16700Schasinglulu #define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */ 2677*91f16700Schasinglulu /* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */ 2678*91f16700Schasinglulu #define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */ 2679*91f16700Schasinglulu /* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */ 2680*91f16700Schasinglulu #define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */ 2681*91f16700Schasinglulu /* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */ 2682*91f16700Schasinglulu #define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */ 2683*91f16700Schasinglulu /* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */ 2684*91f16700Schasinglulu #define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */ 2685*91f16700Schasinglulu /* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */ 2686*91f16700Schasinglulu #define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */ 2687*91f16700Schasinglulu /* PMSR_LAST_DAT (0x10006000+0xF00) */ 2688*91f16700Schasinglulu #define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */ 2689*91f16700Schasinglulu /* PMSR_LAST_CNT (0x10006000+0xF04) */ 2690*91f16700Schasinglulu #define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */ 2691*91f16700Schasinglulu #define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */ 2692*91f16700Schasinglulu /* PMSR_LAST_ACK (0x10006000+0xF08) */ 2693*91f16700Schasinglulu #define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */ 2694*91f16700Schasinglulu /* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */ 2695*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */ 2696*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */ 2697*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */ 2698*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */ 2699*91f16700Schasinglulu /* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */ 2700*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */ 2701*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */ 2702*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */ 2703*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */ 2704*91f16700Schasinglulu /* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */ 2705*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */ 2706*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */ 2707*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */ 2708*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */ 2709*91f16700Schasinglulu /* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */ 2710*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */ 2711*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */ 2712*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */ 2713*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */ 2714*91f16700Schasinglulu /* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */ 2715*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */ 2716*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */ 2717*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */ 2718*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */ 2719*91f16700Schasinglulu /* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */ 2720*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */ 2721*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */ 2722*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */ 2723*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */ 2724*91f16700Schasinglulu /* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */ 2725*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */ 2726*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */ 2727*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */ 2728*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */ 2729*91f16700Schasinglulu /* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */ 2730*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */ 2731*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */ 2732*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */ 2733*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */ 2734*91f16700Schasinglulu /* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */ 2735*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */ 2736*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */ 2737*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */ 2738*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */ 2739*91f16700Schasinglulu /* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */ 2740*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */ 2741*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */ 2742*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */ 2743*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */ 2744*91f16700Schasinglulu /* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */ 2745*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */ 2746*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */ 2747*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */ 2748*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */ 2749*91f16700Schasinglulu /* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */ 2750*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */ 2751*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */ 2752*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */ 2753*91f16700Schasinglulu #define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */ 2754*91f16700Schasinglulu /* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */ 2755*91f16700Schasinglulu #define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */ 2756*91f16700Schasinglulu /* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */ 2757*91f16700Schasinglulu #define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */ 2758*91f16700Schasinglulu /* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */ 2759*91f16700Schasinglulu #define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */ 2760*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */ 2761*91f16700Schasinglulu #define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */ 2762*91f16700Schasinglulu #define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */ 2763*91f16700Schasinglulu #define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */ 2764*91f16700Schasinglulu #define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */ 2765*91f16700Schasinglulu #define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */ 2766*91f16700Schasinglulu #define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */ 2767*91f16700Schasinglulu #define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */ 2768*91f16700Schasinglulu #define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */ 2769*91f16700Schasinglulu #define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */ 2770*91f16700Schasinglulu #define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */ 2771*91f16700Schasinglulu #define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */ 2772*91f16700Schasinglulu #define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */ 2773*91f16700Schasinglulu #define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */ 2774*91f16700Schasinglulu #define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */ 2775*91f16700Schasinglulu #define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */ 2776*91f16700Schasinglulu #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */ 2777*91f16700Schasinglulu #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */ 2778*91f16700Schasinglulu #define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */ 2779*91f16700Schasinglulu #define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */ 2780*91f16700Schasinglulu #define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */ 2781*91f16700Schasinglulu #define PMSR_MODE_LSB (1U << 20) /* 2b */ 2782*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */ 2783*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */ 2784*91f16700Schasinglulu #define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */ 2785*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */ 2786*91f16700Schasinglulu #define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */ 2787*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */ 2788*91f16700Schasinglulu #define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */ 2789*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */ 2790*91f16700Schasinglulu #define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */ 2791*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */ 2792*91f16700Schasinglulu #define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */ 2793*91f16700Schasinglulu /* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */ 2794*91f16700Schasinglulu #define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */ 2795*91f16700Schasinglulu /* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */ 2796*91f16700Schasinglulu #define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */ 2797*91f16700Schasinglulu #define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */ 2798*91f16700Schasinglulu #define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */ 2799*91f16700Schasinglulu /* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */ 2800*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */ 2801*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */ 2802*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */ 2803*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */ 2804*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */ 2805*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */ 2806*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */ 2807*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */ 2808*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */ 2809*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */ 2810*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */ 2811*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */ 2812*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */ 2813*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */ 2814*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */ 2815*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */ 2816*91f16700Schasinglulu /* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */ 2817*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */ 2818*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */ 2819*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */ 2820*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */ 2821*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */ 2822*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */ 2823*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */ 2824*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */ 2825*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */ 2826*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */ 2827*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */ 2828*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */ 2829*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */ 2830*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */ 2831*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */ 2832*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */ 2833*91f16700Schasinglulu /* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */ 2834*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */ 2835*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */ 2836*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */ 2837*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */ 2838*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */ 2839*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */ 2840*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */ 2841*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */ 2842*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */ 2843*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */ 2844*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */ 2845*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */ 2846*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */ 2847*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */ 2848*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */ 2849*91f16700Schasinglulu #define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */ 2850*91f16700Schasinglulu /* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */ 2851*91f16700Schasinglulu #define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */ 2852*91f16700Schasinglulu /* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */ 2853*91f16700Schasinglulu #define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */ 2854*91f16700Schasinglulu /* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */ 2855*91f16700Schasinglulu #define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */ 2856*91f16700Schasinglulu 2857*91f16700Schasinglulu #define SPM_PROJECT_CODE 0xb16 2858*91f16700Schasinglulu #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2859*91f16700Schasinglulu #endif 2860