1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SPM_CONDIT_H 8*91f16700Schasinglulu #define MT_SPM_CONDIT_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <mt_lp_rm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu enum PLAT_SPM_COND { 13*91f16700Schasinglulu PLAT_SPM_COND_MTCMOS1 = 0, 14*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_0, 15*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_1, 16*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_2, 17*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_3, 18*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_4, 19*91f16700Schasinglulu PLAT_SPM_COND_CG_PERI_SW_0, 20*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS0_SW_CG_0, 21*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS0_SW_CG_1, 22*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS0_SW_CG_2, 23*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS1_SW_CG_0, 24*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS1_SW_CG_1, 25*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS0_SW_CG_0, 26*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS0_SW_CG_1, 27*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_SW_CG_0, 28*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_SW_CG_1, 29*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_SW_CG_2, 30*91f16700Schasinglulu PLAT_SPM_COND_CG_I2C_SW_CG, 31*91f16700Schasinglulu PLAT_SPM_COND_MAX, 32*91f16700Schasinglulu }; 33*91f16700Schasinglulu 34*91f16700Schasinglulu enum PLAT_SPM_COND_PLL { 35*91f16700Schasinglulu PLAT_SPM_COND_PLL_UNIVPLL = 0, 36*91f16700Schasinglulu PLAT_SPM_COND_PLL_MFGPLL, 37*91f16700Schasinglulu PLAT_SPM_COND_PLL_MSDCPLL, 38*91f16700Schasinglulu PLAT_SPM_COND_PLL_TVDPLL, 39*91f16700Schasinglulu PLAT_SPM_COND_PLL_MMPLL, 40*91f16700Schasinglulu PLAT_SPM_COND_PLL_MAX, 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL) 44*91f16700Schasinglulu #define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL) 45*91f16700Schasinglulu #define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL) 46*91f16700Schasinglulu #define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL) 47*91f16700Schasinglulu #define PLL_BIT_TVDPLL BIT(PLAT_SPM_COND_PLL_TVDPLL) 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Definition about SPM_COND_CHECK_BLOCKED 50*91f16700Schasinglulu * bit [00 ~ 17]: cg blocking index 51*91f16700Schasinglulu * bit [18 ~ 29]: pll blocking index 52*91f16700Schasinglulu * bit [30] : pll blocking information 53*91f16700Schasinglulu * bit [31] : idle condition check fail 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu #define SPM_COND_BLOCKED_CG_IDX U(0) 56*91f16700Schasinglulu #define SPM_COND_BLOCKED_PLL_IDX U(18) 57*91f16700Schasinglulu #define SPM_COND_CHECK_BLOCKED_PLL BIT(30) 58*91f16700Schasinglulu #define SPM_COND_CHECK_FAIL BIT(31) 59*91f16700Schasinglulu 60*91f16700Schasinglulu struct mt_spm_cond_tables { 61*91f16700Schasinglulu char *name; 62*91f16700Schasinglulu unsigned int table_cg[PLAT_SPM_COND_MAX]; 63*91f16700Schasinglulu unsigned int table_pll; 64*91f16700Schasinglulu void *priv; 65*91f16700Schasinglulu }; 66*91f16700Schasinglulu 67*91f16700Schasinglulu extern unsigned int mt_spm_cond_check(int state_id, 68*91f16700Schasinglulu const struct mt_spm_cond_tables *src, 69*91f16700Schasinglulu const struct mt_spm_cond_tables *dest, 70*91f16700Schasinglulu struct mt_spm_cond_tables *res); 71*91f16700Schasinglulu extern int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num, 72*91f16700Schasinglulu int stateid, void *priv); 73*91f16700Schasinglulu #endif /* MT_SPM_CONDIT_H */ 74