1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 10 #include <mt_lp_rm.h> 11 #include <mt_spm.h> 12 #include <mt_spm_cond.h> 13 #include <mt_spm_constraint.h> 14 #include <mt_spm_conservation.h> 15 #include <mt_spm_idle.h> 16 #include <mt_spm_internal.h> 17 #include <mt_spm_notifier.h> 18 #include <mt_spm_resource_req.h> 19 #include <mt_spm_reg.h> 20 #include <mt_spm_rc_internal.h> 21 #include <mt_spm_suspend.h> 22 #include <plat_pm.h> 23 #include <plat_mtk_lpm.h> 24 25 #define CONSTRAINT_DRAM_ALLOW \ 26 (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \ 27 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \ 28 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF) 29 30 #define CONSTRAINT_DRAM_PCM_FLAG \ 31 (SPM_FLAG_DISABLE_INFRA_PDN | \ 32 SPM_FLAG_DISABLE_VCORE_DVS | \ 33 SPM_FLAG_DISABLE_VCORE_DFS | \ 34 SPM_FLAG_SRAM_SLEEP_CTRL | \ 35 SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \ 36 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP) 37 38 #define CONSTRAINT_DRAM_PCM_FLAG1 0U 39 40 #define CONSTRAINT_DRAM_RESOURCE_REQ \ 41 (MT_SPM_SYSPLL | \ 42 MT_SPM_INFRA | \ 43 MT_SPM_26M) 44 45 static struct mt_spm_cond_tables cond_dram = { 46 .name = "dram", 47 .table_cg = { 48 0xFFFDD008, /* MTCMOS1 */ 49 0x20040802, /* INFRA0 */ 50 0x27AF8000, /* INFRA1 */ 51 0x86040640, /* INFRA2 */ 52 0x00000000, /* INFRA3 */ 53 0x80000000, /* INFRA4 */ 54 0x00000000, /* PERI0 */ 55 0x00004000, /* VPPSYS0_0 */ 56 0x08803000, /* VPPSYS0_1 */ 57 0x00000000, /* VPPSYS0_2 */ 58 0x80005555, /* VPPSYS1_0 */ 59 0x00009008, /* VPPSYS1_1 */ 60 0x60060000, /* VDOSYS0_0 */ 61 0x00000000, /* VDOSYS0_1 */ 62 0x201E01F8, /* VDOSYS1_0 */ 63 0x00800000, /* VDOSYS1_1 */ 64 0x00000000, /* VDOSYS1_2 */ 65 0x00000080, /* I2C */ 66 }, 67 .table_pll = 0U, 68 }; 69 70 static struct mt_spm_cond_tables cond_dram_res = { 71 .table_cg = { 0U }, 72 .table_pll = 0U, 73 }; 74 75 static struct constraint_status status = { 76 .id = MT_RM_CONSTRAINT_ID_DRAM, 77 .valid = (MT_SPM_RC_VALID_SW | 78 MT_SPM_RC_VALID_COND_LATCH | 79 MT_SPM_RC_VALID_XSOC_BBLPM), 80 .cond_block = 0U, 81 .enter_cnt = 0U, 82 .cond_res = &cond_dram_res, 83 }; 84 85 static void spm_dram_conduct(struct spm_lp_scen *spm_lp, 86 unsigned int *resource_req) 87 { 88 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG; 89 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1; 90 *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ; 91 } 92 93 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id) 94 { 95 (void)cpu; 96 (void)state_id; 97 98 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid); 99 } 100 101 int spm_update_rc_dram(int state_id, int type, const void *val) 102 { 103 const struct mt_spm_cond_tables *tlb; 104 const struct mt_spm_cond_tables *tlb_check; 105 int res = MT_RM_STATUS_OK; 106 107 if (val == NULL) { 108 return MT_RM_STATUS_BAD; 109 } 110 111 if (type == PLAT_RC_UPDATE_CONDITION) { 112 tlb = (const struct mt_spm_cond_tables *)val; 113 tlb_check = (const struct mt_spm_cond_tables *)&cond_dram; 114 status.cond_block = 115 mt_spm_cond_check(state_id, tlb, tlb_check, 116 ((status.valid & 117 MT_SPM_RC_VALID_COND_LATCH) != 0U) ? 118 &cond_dram_res : NULL); 119 } else { 120 res = MT_RM_STATUS_BAD; 121 } 122 123 return res; 124 } 125 126 unsigned int spm_allow_rc_dram(int state_id) 127 { 128 (void)state_id; 129 130 return CONSTRAINT_DRAM_ALLOW; 131 } 132 133 int spm_run_rc_dram(unsigned int cpu, int state_id) 134 { 135 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; 136 unsigned int allows = CONSTRAINT_DRAM_ALLOW; 137 138 (void)cpu; 139 140 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { 141 #ifdef MT_SPM_USING_SRCLKEN_RC 142 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; 143 #else 144 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; 145 #endif 146 } 147 148 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT 149 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | 150 (IS_PLAT_SUSPEND_ID(state_id) ? 151 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U)); 152 #else 153 (void)allows; 154 #endif 155 156 if (IS_PLAT_SUSPEND_ID(state_id)) { 157 mt_spm_suspend_enter(state_id, 158 (MT_SPM_EX_OP_SET_WDT | 159 MT_SPM_EX_OP_SET_SUSPEND_MODE | 160 MT_SPM_EX_OP_HW_S1_DETECT), 161 CONSTRAINT_DRAM_RESOURCE_REQ); 162 } else { 163 mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct); 164 } 165 166 return 0; 167 } 168 169 int spm_reset_rc_dram(unsigned int cpu, int state_id) 170 { 171 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT; 172 unsigned int allows = CONSTRAINT_DRAM_ALLOW; 173 174 (void)cpu; 175 176 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) { 177 #ifdef MT_SPM_USING_SRCLKEN_RC 178 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM; 179 #else 180 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM; 181 #endif 182 } 183 184 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT 185 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows); 186 #else 187 (void)allows; 188 #endif 189 190 if (IS_PLAT_SUSPEND_ID(state_id)) { 191 mt_spm_suspend_resume(state_id, 192 (MT_SPM_EX_OP_SET_WDT | 193 MT_SPM_EX_OP_HW_S1_DETECT), 194 NULL); 195 } else { 196 mt_spm_idle_generic_resume(state_id, ext_op, NULL); 197 status.enter_cnt++; 198 } 199 200 return 0; 201 } 202