1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <mtgpio.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu uintptr_t mt_gpio_find_reg_addr(uint32_t pin) 12*91f16700Schasinglulu { 13*91f16700Schasinglulu uintptr_t reg_addr = 0U; 14*91f16700Schasinglulu struct mt_pin_info gpio_info; 15*91f16700Schasinglulu 16*91f16700Schasinglulu assert(pin < MAX_GPIO_PIN); 17*91f16700Schasinglulu 18*91f16700Schasinglulu gpio_info = mt_pin_infos[pin]; 19*91f16700Schasinglulu 20*91f16700Schasinglulu switch (gpio_info.base & 0x0f) { 21*91f16700Schasinglulu case 0: 22*91f16700Schasinglulu reg_addr = IOCFG_BM_BASE; 23*91f16700Schasinglulu break; 24*91f16700Schasinglulu case 1: 25*91f16700Schasinglulu reg_addr = IOCFG_BL_BASE; 26*91f16700Schasinglulu break; 27*91f16700Schasinglulu case 2: 28*91f16700Schasinglulu reg_addr = IOCFG_BR_BASE; 29*91f16700Schasinglulu break; 30*91f16700Schasinglulu case 3: 31*91f16700Schasinglulu reg_addr = IOCFG_LM_BASE; 32*91f16700Schasinglulu break; 33*91f16700Schasinglulu case 4: 34*91f16700Schasinglulu reg_addr = IOCFG_RB_BASE; 35*91f16700Schasinglulu break; 36*91f16700Schasinglulu case 5: 37*91f16700Schasinglulu reg_addr = IOCFG_TL_BASE; 38*91f16700Schasinglulu break; 39*91f16700Schasinglulu default: 40*91f16700Schasinglulu break; 41*91f16700Schasinglulu } 42*91f16700Schasinglulu 43*91f16700Schasinglulu return reg_addr; 44*91f16700Schasinglulu } 45