1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MTK_APUSYS_H 8*91f16700Schasinglulu #define MTK_APUSYS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* setup the SMC command ops */ 13*91f16700Schasinglulu #define MTK_SIP_APU_START_MCU (0x00U) 14*91f16700Schasinglulu #define MTK_SIP_APU_STOP_MCU (0x01U) 15*91f16700Schasinglulu #define MTK_SIP_APUPWR_BUS_PROT_CG_ON (0x02U) 16*91f16700Schasinglulu #define MTK_SIP_APUPWR_BULK_PLL (0x03U) 17*91f16700Schasinglulu #define MTK_SIP_APUPWR_ACC_INIT_ALL (0x04U) 18*91f16700Schasinglulu #define MTK_SIP_APUPWR_ACC_TOP (0x05U) 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* AO Register */ 21*91f16700Schasinglulu #define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) 22*91f16700Schasinglulu #define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) 23*91f16700Schasinglulu #define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) 24*91f16700Schasinglulu #define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) 25*91f16700Schasinglulu #define AO_SEC_USR_FW (APUSYS_APU_S_S_4_BASE + 0x14) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define PRE_DEFINE_CACHE_TCM (0x3U) 28*91f16700Schasinglulu #define PRE_DEFINE_CACHE (0x2U) 29*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_0G (0U) 30*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_1G (2U) 31*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_2G (4U) 32*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_3G (6U) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define SEC_FW_NON_SECURE (1U) 35*91f16700Schasinglulu #define SEC_FW_SHIFT_NS (4U) 36*91f16700Schasinglulu #define SEC_FW_DOMAIN_SHIFT (0U) 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define SEC_USR_FW_NON_SECURE (1U) 39*91f16700Schasinglulu #define SEC_USR_FW_SHIFT_NS (4U) 40*91f16700Schasinglulu #define SEC_USR_FW_DOMAIN_SHIFT (0U) 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define SYS_CTRL_RUN (0U) 43*91f16700Schasinglulu #define SYS_CTRL_STALL (1U) 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* Reviser Register */ 46*91f16700Schasinglulu #define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x100) 47*91f16700Schasinglulu #define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x104) 48*91f16700Schasinglulu 49*91f16700Schasinglulu int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 50*91f16700Schasinglulu uint32_t *ret1); 51*91f16700Schasinglulu #endif /* MTK_APUSYS_H */ 52