1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef APUPWR_CLKCTL_H 8*91f16700Schasinglulu #define APUPWR_CLKCTL_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <apupwr_clkctl_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu int32_t apupwr_smc_acc_init_all(void); 14*91f16700Schasinglulu void apupwr_smc_acc_top(bool enable); 15*91f16700Schasinglulu int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain); 16*91f16700Schasinglulu int32_t apupwr_smc_pll_set_rate(uint32_t pll, bool div2, uint32_t domain); 17*91f16700Schasinglulu int32_t apupwr_smc_bulk_pll(bool enable); 18*91f16700Schasinglulu void apupwr_smc_bus_prot_cg_on(void); 19*91f16700Schasinglulu 20*91f16700Schasinglulu int32_t apu_pll_enable(int32_t pll_idx, bool enable, bool fhctl_en); 21*91f16700Schasinglulu int32_t anpu_pll_set_rate(enum dvfs_voltage_domain domain, 22*91f16700Schasinglulu enum pll_set_rate_mode mode, int32_t freq); 23*91f16700Schasinglulu #endif /* APUPWR_CLKCTL_H */ 24