1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu /**************************************************************** 8*91f16700Schasinglulu * Auto generated by DE, please DO NOT modify this file directly. 9*91f16700Schasinglulu *****************************************************************/ 10*91f16700Schasinglulu #ifndef MT_SPM_PMIC_WRAP_H 11*91f16700Schasinglulu #define MT_SPM_PMIC_WRAP_H 12*91f16700Schasinglulu 13*91f16700Schasinglulu enum pmic_wrap_phase_id { 14*91f16700Schasinglulu PMIC_WRAP_PHASE_ALLINONE, 15*91f16700Schasinglulu NR_PMIC_WRAP_PHASE, 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */ 19*91f16700Schasinglulu enum { 20*91f16700Schasinglulu CMD_0, /* 0x0 */ 21*91f16700Schasinglulu CMD_1, /* 0x1 */ 22*91f16700Schasinglulu CMD_2, /* 0x2 */ 23*91f16700Schasinglulu CMD_3, /* 0x3 */ 24*91f16700Schasinglulu CMD_4, /* 0x4 */ 25*91f16700Schasinglulu CMD_5, /* 0x5 */ 26*91f16700Schasinglulu CMD_6, /* 0x6 */ 27*91f16700Schasinglulu CMD_7, /* 0x7 */ 28*91f16700Schasinglulu CMD_8, /* 0x8 */ 29*91f16700Schasinglulu CMD_9, /* 0x9 */ 30*91f16700Schasinglulu CMD_10, /* 0xA */ 31*91f16700Schasinglulu CMD_11, /* 0xB */ 32*91f16700Schasinglulu CMD_12, /* 0xC */ 33*91f16700Schasinglulu CMD_13, /* 0xD */ 34*91f16700Schasinglulu CMD_14, /* 0xE */ 35*91f16700Schasinglulu CMD_15, /* 0xF */ 36*91f16700Schasinglulu NR_IDX_ALL, 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* APIs */ 40*91f16700Schasinglulu extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); 41*91f16700Schasinglulu extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, 42*91f16700Schasinglulu uint32_t idx, uint32_t cmd_wdata); 43*91f16700Schasinglulu extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, 44*91f16700Schasinglulu uint32_t idx); 45*91f16700Schasinglulu #endif /* MT_SPM_PMIC_WRAP_H */ 46