1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SPM_CONSTRAINT_H 8*91f16700Schasinglulu #define MT_SPM_CONSTRAINT_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <mt_lp_rm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0) 13*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1) 14*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2) 15*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3) 16*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4) 17*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5) 18*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6) 19*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7) 20*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8) 21*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9) 22*91f16700Schasinglulu #define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10) 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define MT_SPM_RC_INVALID 0x0 25*91f16700Schasinglulu #define MT_SPM_RC_VALID_SW (1U << 0) 26*91f16700Schasinglulu #define MT_SPM_RC_VALID_FW (1U << 1) 27*91f16700Schasinglulu #define MT_SPM_RC_VALID_RESIDNECY (1U << 2) 28*91f16700Schasinglulu #define MT_SPM_RC_VALID_COND_CHECK (1U << 3) 29*91f16700Schasinglulu #define MT_SPM_RC_VALID_COND_LATCH (1U << 4) 30*91f16700Schasinglulu #define MT_SPM_RC_VALID_UFS_H8 (1U << 5) 31*91f16700Schasinglulu #define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6) 32*91f16700Schasinglulu #define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7) 33*91f16700Schasinglulu #define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define IS_MT_RM_RC_READY(status) \ 38*91f16700Schasinglulu ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID) 39*91f16700Schasinglulu 40*91f16700Schasinglulu #define MT_SPM_RC_BBLPM_MODE \ 41*91f16700Schasinglulu (MT_SPM_RC_VALID_UFS_H8 | \ 42*91f16700Schasinglulu MT_SPM_RC_VALID_FLIGHTMODE | \ 43*91f16700Schasinglulu MT_SPM_RC_VALID_XSOC_BBLPM) 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define IS_MT_SPM_RC_BBLPM_MODE(st) \ 46*91f16700Schasinglulu ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE) 47*91f16700Schasinglulu 48*91f16700Schasinglulu struct constraint_status { 49*91f16700Schasinglulu uint16_t id; 50*91f16700Schasinglulu uint16_t valid; 51*91f16700Schasinglulu uint32_t cond_block; 52*91f16700Schasinglulu uint32_t enter_cnt; 53*91f16700Schasinglulu struct mt_spm_cond_tables *cond_res; 54*91f16700Schasinglulu }; 55*91f16700Schasinglulu 56*91f16700Schasinglulu enum MT_SPM_RM_RC_TYPE { 57*91f16700Schasinglulu MT_RM_CONSTRAINT_ID_BUS26M, 58*91f16700Schasinglulu MT_RM_CONSTRAINT_ID_SYSPLL, 59*91f16700Schasinglulu MT_RM_CONSTRAINT_ID_DRAM, 60*91f16700Schasinglulu MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO, 61*91f16700Schasinglulu MT_RM_CONSTRAINT_ID_ALL, 62*91f16700Schasinglulu }; 63*91f16700Schasinglulu #endif /* MT_SPM_CONSTRAINT_H */ 64