1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SPM_H 8*91f16700Schasinglulu #define MT_SPM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/bakery_lock.h> 11*91f16700Schasinglulu #include <lib/spinlock.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat_mtk_lpm.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * ARM v8.2, the cache will turn off automatically when cpu 17*91f16700Schasinglulu * power down. So, there is no doubt to use the spin_lock here 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu #if !HW_ASSISTED_COHERENCY 20*91f16700Schasinglulu #define MT_SPM_USING_BAKERY_LOCK 21*91f16700Schasinglulu #endif 22*91f16700Schasinglulu 23*91f16700Schasinglulu #ifdef MT_SPM_USING_BAKERY_LOCK 24*91f16700Schasinglulu DECLARE_BAKERY_LOCK(spm_lock); 25*91f16700Schasinglulu #define plat_spm_lock() bakery_lock_get(&spm_lock) 26*91f16700Schasinglulu #define plat_spm_unlock() bakery_lock_release(&spm_lock) 27*91f16700Schasinglulu #else 28*91f16700Schasinglulu extern spinlock_t spm_lock; 29*91f16700Schasinglulu #define plat_spm_lock() spin_lock(&spm_lock) 30*91f16700Schasinglulu #define plat_spm_unlock() spin_unlock(&spm_lock) 31*91f16700Schasinglulu #endif 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define MT_SPM_USING_SRCLKEN_RC 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* spm extern operand definition */ 36*91f16700Schasinglulu #define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0) 37*91f16700Schasinglulu #define MT_SPM_EX_OP_SET_WDT (1U << 1) 38*91f16700Schasinglulu #define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2) 39*91f16700Schasinglulu #define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3) 40*91f16700Schasinglulu #define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4) 41*91f16700Schasinglulu #define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5) 42*91f16700Schasinglulu #define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6) 43*91f16700Schasinglulu 44*91f16700Schasinglulu typedef enum { 45*91f16700Schasinglulu WR_NONE = 0, 46*91f16700Schasinglulu WR_UART_BUSY = 1, 47*91f16700Schasinglulu WR_ABORT = 2, 48*91f16700Schasinglulu WR_PCM_TIMER = 3, 49*91f16700Schasinglulu WR_WAKE_SRC = 4, 50*91f16700Schasinglulu WR_DVFSRC = 5, 51*91f16700Schasinglulu WR_TWAM = 6, 52*91f16700Schasinglulu WR_PMSR = 7, 53*91f16700Schasinglulu WR_SPM_ACK_CHK = 8, 54*91f16700Schasinglulu WR_UNKNOWN = 9, 55*91f16700Schasinglulu } wake_reason_t; 56*91f16700Schasinglulu 57*91f16700Schasinglulu static inline void spm_lock_get(void) 58*91f16700Schasinglulu { 59*91f16700Schasinglulu plat_spm_lock(); 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu static inline void spm_lock_release(void) 63*91f16700Schasinglulu { 64*91f16700Schasinglulu plat_spm_unlock(); 65*91f16700Schasinglulu } 66*91f16700Schasinglulu 67*91f16700Schasinglulu extern void spm_boot_init(void); 68*91f16700Schasinglulu #endif /* MT_SPM_H */ 69