1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stddef.h> 8*91f16700Schasinglulu #include <string.h> 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/bakery_lock.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu #include <mt_lp_rm.h> 13*91f16700Schasinglulu #include <mt_spm.h> 14*91f16700Schasinglulu #include <mt_spm_cond.h> 15*91f16700Schasinglulu #include <mt_spm_conservation.h> 16*91f16700Schasinglulu #include <mt_spm_constraint.h> 17*91f16700Schasinglulu #include <mt_spm_idle.h> 18*91f16700Schasinglulu #include <mt_spm_internal.h> 19*91f16700Schasinglulu #include <mt_spm_pmic_wrap.h> 20*91f16700Schasinglulu #include <mt_spm_rc_internal.h> 21*91f16700Schasinglulu #include <mt_spm_reg.h> 22*91f16700Schasinglulu #include <mt_spm_resource_req.h> 23*91f16700Schasinglulu #include <mt_spm_suspend.h> 24*91f16700Schasinglulu #include <mtk_plat_common.h> 25*91f16700Schasinglulu #include <plat_mtk_lpm.h> 26*91f16700Schasinglulu #include <plat_pm.h> 27*91f16700Schasinglulu #include <platform_def.h> 28*91f16700Schasinglulu #include <sleep_def.h> 29*91f16700Schasinglulu 30*91f16700Schasinglulu #ifdef MT_SPM_USING_BAKERY_LOCK 31*91f16700Schasinglulu DEFINE_BAKERY_LOCK(spm_lock); 32*91f16700Schasinglulu #define plat_spm_lock_init() bakery_lock_init(&spm_lock) 33*91f16700Schasinglulu #else 34*91f16700Schasinglulu spinlock_t spm_lock; 35*91f16700Schasinglulu #define plat_spm_lock_init() 36*91f16700Schasinglulu #endif 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* CLK_SCP_CFG_0 */ 39*91f16700Schasinglulu #define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200) 40*91f16700Schasinglulu #define SPM_CK_CONTROL_EN 0x3FF 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* CLK_SCP_CFG_1 */ 43*91f16700Schasinglulu #define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210) 44*91f16700Schasinglulu #define CLK_SCP_CFG_1_MASK 0x100C 45*91f16700Schasinglulu #define CLK_SCP_CFG_1_SPM 0x3 46*91f16700Schasinglulu 47*91f16700Schasinglulu struct mt_resource_constraint plat_constraint_bus26m = { 48*91f16700Schasinglulu .is_valid = spm_is_valid_rc_bus26m, 49*91f16700Schasinglulu .update = spm_update_rc_bus26m, 50*91f16700Schasinglulu .allow = spm_allow_rc_bus26m, 51*91f16700Schasinglulu .run = spm_run_rc_bus26m, 52*91f16700Schasinglulu .reset = spm_reset_rc_bus26m, 53*91f16700Schasinglulu }; 54*91f16700Schasinglulu 55*91f16700Schasinglulu struct mt_resource_constraint plat_constraint_syspll = { 56*91f16700Schasinglulu .is_valid = spm_is_valid_rc_syspll, 57*91f16700Schasinglulu .update = spm_update_rc_syspll, 58*91f16700Schasinglulu .allow = spm_allow_rc_syspll, 59*91f16700Schasinglulu .run = spm_run_rc_syspll, 60*91f16700Schasinglulu .reset = spm_reset_rc_syspll, 61*91f16700Schasinglulu }; 62*91f16700Schasinglulu 63*91f16700Schasinglulu struct mt_resource_constraint plat_constraint_dram = { 64*91f16700Schasinglulu .is_valid = spm_is_valid_rc_dram, 65*91f16700Schasinglulu .update = spm_update_rc_dram, 66*91f16700Schasinglulu .allow = spm_allow_rc_dram, 67*91f16700Schasinglulu .run = spm_run_rc_dram, 68*91f16700Schasinglulu .reset = spm_reset_rc_dram, 69*91f16700Schasinglulu }; 70*91f16700Schasinglulu 71*91f16700Schasinglulu struct mt_resource_constraint plat_constraint_cpu = { 72*91f16700Schasinglulu .is_valid = spm_is_valid_rc_cpu_buck_ldo, 73*91f16700Schasinglulu .update = NULL, 74*91f16700Schasinglulu .allow = spm_allow_rc_cpu_buck_ldo, 75*91f16700Schasinglulu .run = spm_run_rc_cpu_buck_ldo, 76*91f16700Schasinglulu .reset = spm_reset_rc_cpu_buck_ldo, 77*91f16700Schasinglulu }; 78*91f16700Schasinglulu 79*91f16700Schasinglulu struct mt_resource_constraint *plat_constraints[] = { 80*91f16700Schasinglulu &plat_constraint_bus26m, 81*91f16700Schasinglulu &plat_constraint_syspll, 82*91f16700Schasinglulu &plat_constraint_dram, 83*91f16700Schasinglulu &plat_constraint_cpu, 84*91f16700Schasinglulu NULL, 85*91f16700Schasinglulu }; 86*91f16700Schasinglulu 87*91f16700Schasinglulu struct mt_resource_manager plat_mt8192_rm = { 88*91f16700Schasinglulu .update = mt_spm_cond_update, 89*91f16700Schasinglulu .consts = plat_constraints, 90*91f16700Schasinglulu }; 91*91f16700Schasinglulu 92*91f16700Schasinglulu void spm_boot_init(void) 93*91f16700Schasinglulu { 94*91f16700Schasinglulu /* switch ck_off/axi_26m control to SPM */ 95*91f16700Schasinglulu mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN); 96*91f16700Schasinglulu mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, 97*91f16700Schasinglulu CLK_SCP_CFG_1_SPM); 98*91f16700Schasinglulu 99*91f16700Schasinglulu plat_spm_lock_init(); 100*91f16700Schasinglulu mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE); 101*91f16700Schasinglulu mt_lp_rm_register(&plat_mt8192_rm); 102*91f16700Schasinglulu mt_spm_idle_generic_init(); 103*91f16700Schasinglulu mt_spm_suspend_init(); 104*91f16700Schasinglulu } 105