xref: /arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef MTK_DCM_UTILS_H
8*91f16700Schasinglulu #define MTK_DCM_UTILS_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <stdbool.h>
11*91f16700Schasinglulu 
12*91f16700Schasinglulu #include <mtk_dcm.h>
13*91f16700Schasinglulu #include <platform_def.h>
14*91f16700Schasinglulu 
15*91f16700Schasinglulu /* Base */
16*91f16700Schasinglulu #define MP_CPUSYS_TOP_BASE	(MCUCFG_BASE + 0x8000)
17*91f16700Schasinglulu #define CPCCFG_REG_BASE		(MCUCFG_BASE + 0xA800)
18*91f16700Schasinglulu 
19*91f16700Schasinglulu /* Register Definition */
20*91f16700Schasinglulu #define CPU_PLLDIV_CFG0		(MP_CPUSYS_TOP_BASE + 0x22a0)
21*91f16700Schasinglulu #define CPU_PLLDIV_CFG1		(MP_CPUSYS_TOP_BASE + 0x22a4)
22*91f16700Schasinglulu #define CPU_PLLDIV_CFG2		(MP_CPUSYS_TOP_BASE + 0x22a8)
23*91f16700Schasinglulu #define CPU_PLLDIV_CFG3		(MP_CPUSYS_TOP_BASE + 0x22ac)
24*91f16700Schasinglulu #define CPU_PLLDIV_CFG4		(MP_CPUSYS_TOP_BASE + 0x22b0)
25*91f16700Schasinglulu #define BUS_PLLDIV_CFG		(MP_CPUSYS_TOP_BASE + 0x22e0)
26*91f16700Schasinglulu #define MCSI_DCM0		(MP_CPUSYS_TOP_BASE + 0x2440)
27*91f16700Schasinglulu #define MP_ADB_DCM_CFG0		(MP_CPUSYS_TOP_BASE + 0x2500)
28*91f16700Schasinglulu #define MP_ADB_DCM_CFG4		(MP_CPUSYS_TOP_BASE + 0x2510)
29*91f16700Schasinglulu #define MP_MISC_DCM_CFG0	(MP_CPUSYS_TOP_BASE + 0x2518)
30*91f16700Schasinglulu #define MCUSYS_DCM_CFG0		(MP_CPUSYS_TOP_BASE + 0x25c0)
31*91f16700Schasinglulu #define EMI_WFIFO		(CPCCFG_REG_BASE + 0x100)
32*91f16700Schasinglulu #define MP0_DCM_CFG0		(MP_CPUSYS_TOP_BASE + 0x4880)
33*91f16700Schasinglulu #define MP0_DCM_CFG7		(MP_CPUSYS_TOP_BASE + 0x489c)
34*91f16700Schasinglulu 
35*91f16700Schasinglulu /* MP_CPUSYS_TOP */
36*91f16700Schasinglulu bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
37*91f16700Schasinglulu void dcm_mp_cpusys_top_adb_dcm(bool on);
38*91f16700Schasinglulu bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
39*91f16700Schasinglulu void dcm_mp_cpusys_top_apb_dcm(bool on);
40*91f16700Schasinglulu bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
41*91f16700Schasinglulu void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
42*91f16700Schasinglulu bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
43*91f16700Schasinglulu void dcm_mp_cpusys_top_core_stall_dcm(bool on);
44*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
45*91f16700Schasinglulu void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
46*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
47*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
48*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
49*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
50*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void);
51*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on);
52*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void);
53*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on);
54*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void);
55*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on);
56*91f16700Schasinglulu bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
57*91f16700Schasinglulu void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
58*91f16700Schasinglulu bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
59*91f16700Schasinglulu void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
60*91f16700Schasinglulu bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
61*91f16700Schasinglulu void dcm_mp_cpusys_top_misc_dcm(bool on);
62*91f16700Schasinglulu bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
63*91f16700Schasinglulu void dcm_mp_cpusys_top_mp0_qdcm(bool on);
64*91f16700Schasinglulu /* CPCCFG_REG */
65*91f16700Schasinglulu bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
66*91f16700Schasinglulu void dcm_cpccfg_reg_emi_wfifo(bool on);
67*91f16700Schasinglulu 
68*91f16700Schasinglulu #endif
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