1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <mtk_dcm.h> 8*91f16700Schasinglulu #include <mtk_dcm_utils.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu static void dcm_armcore(bool mode) 11*91f16700Schasinglulu { 12*91f16700Schasinglulu dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 13*91f16700Schasinglulu dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 14*91f16700Schasinglulu dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 15*91f16700Schasinglulu } 16*91f16700Schasinglulu 17*91f16700Schasinglulu static void dcm_mcusys(bool on) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu dcm_mp_cpusys_top_adb_dcm(on); 20*91f16700Schasinglulu dcm_mp_cpusys_top_apb_dcm(on); 21*91f16700Schasinglulu dcm_mp_cpusys_top_cpubiu_dcm(on); 22*91f16700Schasinglulu dcm_mp_cpusys_top_misc_dcm(on); 23*91f16700Schasinglulu dcm_mp_cpusys_top_mp0_qdcm(on); 24*91f16700Schasinglulu dcm_cpccfg_reg_emi_wfifo(on); 25*91f16700Schasinglulu dcm_mp_cpusys_top_last_cor_idle_dcm(on); 26*91f16700Schasinglulu } 27*91f16700Schasinglulu 28*91f16700Schasinglulu static void dcm_stall(bool on) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu dcm_mp_cpusys_top_core_stall_dcm(on); 31*91f16700Schasinglulu dcm_mp_cpusys_top_fcm_stall_dcm(on); 32*91f16700Schasinglulu } 33*91f16700Schasinglulu 34*91f16700Schasinglulu static bool check_dcm_state(void) 35*91f16700Schasinglulu { 36*91f16700Schasinglulu bool ret = true; 37*91f16700Schasinglulu 38*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 39*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 40*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 41*91f16700Schasinglulu 42*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 43*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 44*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 45*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 46*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 47*91f16700Schasinglulu ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 48*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 49*91f16700Schasinglulu 50*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 51*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 52*91f16700Schasinglulu 53*91f16700Schasinglulu return ret; 54*91f16700Schasinglulu } 55*91f16700Schasinglulu 56*91f16700Schasinglulu bool dcm_set_default(void) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu dcm_armcore(true); 59*91f16700Schasinglulu dcm_mcusys(true); 60*91f16700Schasinglulu dcm_stall(true); 61*91f16700Schasinglulu 62*91f16700Schasinglulu return check_dcm_state(); 63*91f16700Schasinglulu } 64