1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __MTK_APUSYS_H__ 8*91f16700Schasinglulu #define __MTK_APUSYS_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* setup the SMC command ops */ 13*91f16700Schasinglulu #define MTK_SIP_APU_START_MCU 0x00U 14*91f16700Schasinglulu #define MTK_SIP_APU_STOP_MCU 0x01U 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* AO Register */ 17*91f16700Schasinglulu #define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) 18*91f16700Schasinglulu #define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) 19*91f16700Schasinglulu #define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) 20*91f16700Schasinglulu #define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define PRE_DEFINE_CACHE_TCM 0x3U 23*91f16700Schasinglulu #define PRE_DEFINE_CACHE 0x2U 24*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_0G 0U 25*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_1G 2U 26*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_2G 4U 27*91f16700Schasinglulu #define PRE_DEFINE_SHIFT_3G 6U 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define SEC_FW_NON_SECURE 1U 30*91f16700Schasinglulu #define SEC_FW_SHIFT_NS 4U 31*91f16700Schasinglulu #define SEC_FW_DOMAIN_SHIFT 0U 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define SYS_CTRL_RUN 0U 34*91f16700Schasinglulu #define SYS_CTRL_STALL 1U 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* Reviser Register */ 37*91f16700Schasinglulu #define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300) 38*91f16700Schasinglulu #define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304) 39*91f16700Schasinglulu 40*91f16700Schasinglulu uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 41*91f16700Schasinglulu uint32_t *ret1); 42*91f16700Schasinglulu #endif /* __MTK_APUSYS_H__ */ 43