1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu /* Project Includes */ 8*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_v2.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Platform Includes */ 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Table of regions to map using the MMU. */ 14*91f16700Schasinglulu const mmap_region_t plat_mmap[] = { 15*91f16700Schasinglulu /* for TF text, RO, RW */ 16*91f16700Schasinglulu MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 17*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 18*91f16700Schasinglulu MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 19*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 20*91f16700Schasinglulu MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE, 21*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 22*91f16700Schasinglulu MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE, 23*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 24*91f16700Schasinglulu MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE, 25*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 26*91f16700Schasinglulu MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE, 27*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 28*91f16700Schasinglulu MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE, 29*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 30*91f16700Schasinglulu MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE, 31*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE), 32*91f16700Schasinglulu { 0 } 33*91f16700Schasinglulu }; 34*91f16700Schasinglulu 35*91f16700Schasinglulu /******************************************************************************* 36*91f16700Schasinglulu * Macro generating the code for the function setting up the pagetables as per 37*91f16700Schasinglulu * the platform memory map & initialize the mmu, for the given exception level 38*91f16700Schasinglulu ******************************************************************************/ 39*91f16700Schasinglulu void plat_configure_mmu_el3(uintptr_t total_base, 40*91f16700Schasinglulu uintptr_t total_size, 41*91f16700Schasinglulu uintptr_t ro_start, 42*91f16700Schasinglulu uintptr_t ro_limit) 43*91f16700Schasinglulu { 44*91f16700Schasinglulu mmap_add_region(total_base, total_base, total_size, 45*91f16700Schasinglulu MT_RW_DATA | MT_SECURE); 46*91f16700Schasinglulu mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 47*91f16700Schasinglulu MT_CODE | MT_SECURE); 48*91f16700Schasinglulu mmap_add(plat_mmap); 49*91f16700Schasinglulu init_xlat_tables(); 50*91f16700Schasinglulu enable_mmu_el3(0); 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu return SYS_COUNTER_FREQ_IN_TICKS; 56*91f16700Schasinglulu } 57