1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl plat_is_my_cpu_primary 12*91f16700Schasinglulu .globl plat_my_core_pos 13*91f16700Schasinglulu .globl plat_mediatek_calc_core_pos 14*91f16700Schasinglulu 15*91f16700Schasinglulufunc plat_is_my_cpu_primary 16*91f16700Schasinglulu mrs x0, mpidr_el1 17*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 18*91f16700Schasinglulu cmp x0, #PLAT_PRIMARY_CPU 19*91f16700Schasinglulu cset x0, eq 20*91f16700Schasinglulu ret 21*91f16700Schasingluluendfunc plat_is_my_cpu_primary 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* ----------------------------------------------------- 24*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 25*91f16700Schasinglulu * This function uses the plat_mediatek_calc_core_pos() 26*91f16700Schasinglulu * definition to get the index of the calling CPU. 27*91f16700Schasinglulu * ----------------------------------------------------- 28*91f16700Schasinglulu */ 29*91f16700Schasinglulufunc plat_my_core_pos 30*91f16700Schasinglulu mrs x0, mpidr_el1 31*91f16700Schasinglulu b plat_mediatek_calc_core_pos 32*91f16700Schasingluluendfunc plat_my_core_pos 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* ----------------------------------------------------- 35*91f16700Schasinglulu * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr); 36*91f16700Schasinglulu * 37*91f16700Schasinglulu * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and 38*91f16700Schasinglulu * AFF0 is thread id. There is only one cluster in ARMv8.2 39*91f16700Schasinglulu * and one thread in current implementation. 40*91f16700Schasinglulu * 41*91f16700Schasinglulu * With this function: CorePos = CoreID (AFF1) 42*91f16700Schasinglulu * we do it with x0 = (x0 >> 8) & 0xff 43*91f16700Schasinglulu * ----------------------------------------------------- 44*91f16700Schasinglulu */ 45*91f16700Schasinglulufunc plat_mediatek_calc_core_pos 46*91f16700Schasinglulu mov x1, #MPIDR_AFFLVL_MASK 47*91f16700Schasinglulu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 48*91f16700Schasinglulu ret 49*91f16700Schasingluluendfunc plat_mediatek_calc_core_pos 50