1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __PLAT_UART_H__ 8*91f16700Schasinglulu #define __PLAT_UART_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* UART error code */ 11*91f16700Schasinglulu #define UART_DONE U(0) 12*91f16700Schasinglulu #define UART_PM_ERROR U(1) 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* UART HW information */ 15*91f16700Schasinglulu #ifndef HW_SUPPORT_UART_PORTS 16*91f16700Schasinglulu #define HW_SUPPORT_UART_PORTS (2U) /* the UART PORTs current HW have */ 17*91f16700Schasinglulu #endif 18*91f16700Schasinglulu #define MTK_UART_SEND_SLEEP_REQ (1U) /* Request uart to sleep */ 19*91f16700Schasinglulu #define MTK_UART_SLEEP_ACK_IDLE (1U) /* uart in idle state */ 20*91f16700Schasinglulu #define MTK_UART_WAIT_ACK_TIMES (50U) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define UART_BASE0 (0x11002000) 23*91f16700Schasinglulu #define UART_BASE1 (0x11003000) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #endif /* __PLAT_UART_H__ */ 26