1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_PM_H 8*91f16700Schasinglulu #define PLAT_PM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #ifndef __ASSEMBLY__ 13*91f16700Schasinglulu extern uintptr_t mtk_suspend_footprint_addr; 14*91f16700Schasinglulu extern uintptr_t mtk_suspend_timestamp_addr; 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define MT_PLAT_PWR_STATE_CPU U(1) 17*91f16700Schasinglulu #define MT_PLAT_PWR_STATE_CLUSTER U(2) 18*91f16700Schasinglulu #define MT_PLAT_PWR_STATE_MCUSYS U(3) 19*91f16700Schasinglulu #define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8) 20*91f16700Schasinglulu #define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define MTK_LOCAL_STATE_RUN U(0) 23*91f16700Schasinglulu #define MTK_LOCAL_STATE_RET U(1) 24*91f16700Schasinglulu #define MTK_LOCAL_STATE_OFF U(2) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define MTK_AFFLVL_CPU U(0) 27*91f16700Schasinglulu #define MTK_AFFLVL_CLUSTER U(1) 28*91f16700Schasinglulu #define MTK_AFFLVL_MCUSYS U(2) 29*91f16700Schasinglulu #define MTK_AFFLVL_SYSTEM U(3) 30*91f16700Schasinglulu 31*91f16700Schasinglulu void mtk_suspend_footprint_log(int idx); 32*91f16700Schasinglulu void mtk_suspend_timestamp_log(int idx); 33*91f16700Schasinglulu 34*91f16700Schasinglulu int mt_cluster_ops(int cputop_mpx, int mode, int state); 35*91f16700Schasinglulu int mt_core_ops(int cpux, int state); 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define IS_CLUSTER_OFF_STATE(s) \ 38*91f16700Schasinglulu is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER]) 39*91f16700Schasinglulu #define IS_MCUSYS_OFF_STATE(s) \ 40*91f16700Schasinglulu is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS]) 41*91f16700Schasinglulu #define IS_SYSTEM_SUSPEND_STATE(s) \ 42*91f16700Schasinglulu is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM]) 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* SMC secure magic number */ 45*91f16700Schasinglulu #define SPM_LP_SMC_MAGIC (0xDAF10000) 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define IS_SPM_LP_SMC(_type, _id) (_id == (SPM_LP_SMC_MAGIC | _type)) 48*91f16700Schasinglulu 49*91f16700Schasinglulu enum mtk_suspend_mode { 50*91f16700Schasinglulu MTK_MCDI_MODE = 1U, 51*91f16700Schasinglulu MTK_IDLEDRAM_MODE = 2U, 52*91f16700Schasinglulu MTK_IDLESYSPLL_MODE = 3U, 53*91f16700Schasinglulu MTK_IDLEBUS26M_MODE = 4U, 54*91f16700Schasinglulu MTK_SUSPEND_MODE = 5U, 55*91f16700Schasinglulu }; 56*91f16700Schasinglulu #endif 57*91f16700Schasinglulu 58*91f16700Schasinglulu enum mt8169_idle_model { 59*91f16700Schasinglulu IDLE_MODEL_START = 0U, 60*91f16700Schasinglulu IDLE_MODEL_RESOURCE_HEAD = IDLE_MODEL_START, 61*91f16700Schasinglulu IDLE_MODEL_BUS26M = IDLE_MODEL_RESOURCE_HEAD, 62*91f16700Schasinglulu IDLE_MODEL_SYSPLL = 1U, 63*91f16700Schasinglulu IDLE_MODEL_DRAM = 2U, 64*91f16700Schasinglulu IDLE_MODEL_NUM = 3U, 65*91f16700Schasinglulu }; 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define footprint_addr(cpu) (mtk_suspend_footprint_addr + (cpu << 2)) 68*91f16700Schasinglulu #define timestamp_addr(cpu, idx) (mtk_suspend_timestamp_addr + \ 69*91f16700Schasinglulu ((cpu * MTK_SUSPEND_TIMESTAMP_MAX + idx) << 3)) 70*91f16700Schasinglulu 71*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_ENTER_CPUIDLE (0U) 72*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_BEFORE_ATF (1U) 73*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_ENTER_ATF (2U) 74*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_RESERVE_P1 (3U) 75*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_RESERVE_P2 (4U) 76*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND (5U) 77*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND (6U) 78*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_BEFORE_WFI (7U) 79*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_AFTER_WFI (8U) 80*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_BEFORE_MMU (9U) 81*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_AFTER_MMU (10U) 82*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND_FINISH (11U) 83*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND_FINISH (12U) 84*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_LEAVE_ATF (13U) 85*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_AFTER_ATF (14U) 86*91f16700Schasinglulu #define MTK_SUSPEND_FOOTPRINT_LEAVE_CPUIDLE (15U) 87*91f16700Schasinglulu 88*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_ENTER_CPUIDLE (0U) 89*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_BEFORE_ATF (1U) 90*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_ENTER_ATF (2U) 91*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_BEFORE_L2_FLUSH (3U) 92*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_AFTER_L2_FLUSH (4U) 93*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND (5U) 94*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND (6U) 95*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_GIC_P1 (7U) 96*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_GIC_P2 (8U) 97*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_BEFORE_WFI (9U) 98*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_AFTER_WFI (10U) 99*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_RESERVE_P1 (11U) 100*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_RESERVE_P2 (12U) 101*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_GIC_P3 (13U) 102*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_GIC_P4 (14U) 103*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND_FINISH (15U) 104*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND_FINISH (16U) 105*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_LEAVE_ATF (17U) 106*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_AFTER_ATF (18U) 107*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_LEAVE_CPUIDLE (19U) 108*91f16700Schasinglulu #define MTK_SUSPEND_TIMESTAMP_MAX (20U) 109*91f16700Schasinglulu 110*91f16700Schasinglulu /* 111*91f16700Schasinglulu * definition platform power state menas. 112*91f16700Schasinglulu * PLAT_MT_SYSTEM_SUSPEND - system suspend pwr level 113*91f16700Schasinglulu * PLAT_MT_CPU_SUSPEND_CLUSTER - cluster off pwr level 114*91f16700Schasinglulu */ 115*91f16700Schasinglulu #define PLAT_MT_SYSTEM_SUSPEND PLAT_MAX_OFF_STATE 116*91f16700Schasinglulu #define PLAT_MT_CPU_SUSPEND_CLUSTER PLAT_MAX_RET_STATE 117*91f16700Schasinglulu 118*91f16700Schasinglulu #define IS_PLAT_SYSTEM_SUSPEND(aff) (aff == PLAT_MT_SYSTEM_SUSPEND) 119*91f16700Schasinglulu #define IS_PLAT_SYSTEM_RETENTION(aff) (aff >= PLAT_MAX_RET_STATE) 120*91f16700Schasinglulu 121*91f16700Schasinglulu #define IS_PLAT_SUSPEND2IDLE_ID(stateid)\ 122*91f16700Schasinglulu (stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) 123*91f16700Schasinglulu 124*91f16700Schasinglulu #define IS_PLAT_SUSPEND_ID(stateid) \ 125*91f16700Schasinglulu ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \ 126*91f16700Schasinglulu || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND)) 127*91f16700Schasinglulu 128*91f16700Schasinglulu #endif /* PLAT_PM_H */ 129