1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu /**************************************************************** 8*91f16700Schasinglulu * Auto generated by DE, please DO NOT modify this file directly. 9*91f16700Schasinglulu *****************************************************************/ 10*91f16700Schasinglulu #ifndef MT_SPM_PMIC_WRAP_H 11*91f16700Schasinglulu #define MT_SPM_PMIC_WRAP_H 12*91f16700Schasinglulu 13*91f16700Schasinglulu enum pmic_wrap_phase_id { 14*91f16700Schasinglulu PMIC_WRAP_PHASE_ALLINONE = 0U, 15*91f16700Schasinglulu NR_PMIC_WRAP_PHASE = 1U, 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */ 19*91f16700Schasinglulu enum { 20*91f16700Schasinglulu CMD_0 = 0U, /* 0x0 */ 21*91f16700Schasinglulu CMD_1 = 1U, /* 0x1 */ 22*91f16700Schasinglulu CMD_2 = 2U, /* 0x2 */ 23*91f16700Schasinglulu CMD_3 = 3U, /* 0x3 */ 24*91f16700Schasinglulu CMD_4 = 4U, /* 0x4 */ 25*91f16700Schasinglulu CMD_5 = 5U, /* 0x5 */ 26*91f16700Schasinglulu CMD_6 = 6U, /* 0x6 */ 27*91f16700Schasinglulu CMD_7 = 7U, /* 0x7 */ 28*91f16700Schasinglulu CMD_8 = 8U, /* 0x8 */ 29*91f16700Schasinglulu NR_IDX_ALL = 9U, 30*91f16700Schasinglulu }; 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* APIs */ 33*91f16700Schasinglulu extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); 34*91f16700Schasinglulu extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, 35*91f16700Schasinglulu uint32_t idx, uint32_t cmd_wdata); 36*91f16700Schasinglulu extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, 37*91f16700Schasinglulu uint32_t idx); 38*91f16700Schasinglulu 39*91f16700Schasinglulu #endif /* MT_SPM_PMIC_WRAP_H */ 40