1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __MT_CPU_PM_H__ 8*91f16700Schasinglulu #define __MT_CPU_PM_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define MCUSYS_STATUS_PDN (1 << 0UL) 11*91f16700Schasinglulu #define MCUSYS_STATUS_CPUSYS_PROTECT (1 << 8UL) 12*91f16700Schasinglulu #define MCUSYS_STATUS_MCUSYS_PROTECT (1 << 9UL) 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* cpu_pm function ID*/ 15*91f16700Schasinglulu enum mt_cpu_pm_user_id { 16*91f16700Schasinglulu MCUSYS_STATUS, 17*91f16700Schasinglulu CPC_COMMAND, 18*91f16700Schasinglulu IRQ_REMAIN_LIST_ALLOC, 19*91f16700Schasinglulu IRQ_REMAIN_IRQ_ADD, 20*91f16700Schasinglulu IRQ_REMAIN_IRQ_SUBMIT, 21*91f16700Schasinglulu MBOX_INFO, 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* cpu_pm lp function ID */ 25*91f16700Schasinglulu enum mt_cpu_pm_lp_smc_id { 26*91f16700Schasinglulu LP_CPC_COMMAND, 27*91f16700Schasinglulu IRQS_REMAIN_ALLOC, 28*91f16700Schasinglulu IRQS_REMAIN_CTRL, 29*91f16700Schasinglulu IRQS_REMAIN_IRQ, 30*91f16700Schasinglulu IRQS_REMAIN_WAKEUP_CAT, 31*91f16700Schasinglulu IRQS_REMAIN_WAKEUP_SRC, 32*91f16700Schasinglulu }; 33*91f16700Schasinglulu 34*91f16700Schasinglulu #endif 35