1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DFD_H 8*91f16700Schasinglulu #define PLAT_DFD_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ 15*91f16700Schasinglulu dsbsy(); \ 16*91f16700Schasinglulu } while (0) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) 19*91f16700Schasinglulu #define PLAT_MTK_DFD_READ_MAGIC (0x99716151) 20*91f16700Schasinglulu #define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define MCU_BIU_BASE (MCUCFG_BASE) 23*91f16700Schasinglulu #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xA040) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) 26*91f16700Schasinglulu #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) 27*91f16700Schasinglulu #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) 28*91f16700Schasinglulu #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) 29*91f16700Schasinglulu #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) 30*91f16700Schasinglulu #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) 31*91f16700Schasinglulu #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) 32*91f16700Schasinglulu #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) 33*91f16700Schasinglulu #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) 34*91f16700Schasinglulu #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) 35*91f16700Schasinglulu #define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define DFD_V35_ENALBE (MCU_BIU_BASE + 0xA0A8) 38*91f16700Schasinglulu #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xA0AC) 39*91f16700Schasinglulu #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xA0B0) 40*91f16700Schasinglulu #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xA0C0) 41*91f16700Schasinglulu #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xA0C4) 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define DFD_CACHE_DUMP_ENABLE (1U) 44*91f16700Schasinglulu #define DFD_PARITY_ERR_TRIGGER (2U) 45*91f16700Schasinglulu 46*91f16700Schasinglulu #define MCUSYS_DFD_MAP (0x10001390) 47*91f16700Schasinglulu #define WDT_DEBUG_CTL (0x10007048) 48*91f16700Schasinglulu 49*91f16700Schasinglulu #define WDT_DEBUG_CTL_VAL_0 (0x950603A0) 50*91f16700Schasinglulu #define DFD_INTERNAL_TEST_SO_0_VAL (0x3B) 51*91f16700Schasinglulu #define DFD_TEST_SI_0_VAL (0x108) 52*91f16700Schasinglulu #define DFD_TEST_SI_1_VAL (0x20200000) 53*91f16700Schasinglulu 54*91f16700Schasinglulu #define WDT_DEBUG_CTL_VAL_1 (0x95063E80) 55*91f16700Schasinglulu #define DFD_V35_TAP_NUMBER_VAL (0xA) 56*91f16700Schasinglulu #define DFD_V35_TAP_EN_VAL (0x3FF) 57*91f16700Schasinglulu #define DFD_V35_SEQ0_0_VAL (0x63668820) 58*91f16700Schasinglulu #define DFD_HW_TRIGGER_MASK_VAL (0xC) 59*91f16700Schasinglulu 60*91f16700Schasinglulu void dfd_resume(void); 61*91f16700Schasinglulu uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 62*91f16700Schasinglulu uint64_t arg2, uint64_t arg3); 63*91f16700Schasinglulu 64*91f16700Schasinglulu #endif /* PLAT_DFD_H */ 65