1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu #include <mtk_sip_svc.h> 11*91f16700Schasinglulu #include <plat_dfd.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu static bool dfd_enabled; 14*91f16700Schasinglulu static uint64_t dfd_base_addr; 15*91f16700Schasinglulu static uint64_t dfd_chain_length; 16*91f16700Schasinglulu static uint64_t dfd_cache_dump; 17*91f16700Schasinglulu 18*91f16700Schasinglulu static void dfd_setup(uint64_t base_addr, uint64_t chain_length, 19*91f16700Schasinglulu uint64_t cache_dump) 20*91f16700Schasinglulu { 21*91f16700Schasinglulu mmio_write_32(MCUSYS_DFD_MAP, base_addr >> 24); 22*91f16700Schasinglulu mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_0); 23*91f16700Schasinglulu 24*91f16700Schasinglulu sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2))); 25*91f16700Schasinglulu 26*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); 27*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3)); 28*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20))); 29*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_PWR_ON, (BIT(0) | BIT(1) | BIT(3))); 30*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 31*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0); 32*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_TEST_SO_0, DFD_INTERNAL_TEST_SO_0_VAL); 33*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 1); 34*91f16700Schasinglulu 35*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_VAL); 36*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL); 37*91f16700Schasinglulu 38*91f16700Schasinglulu sync_writel(DFD_V30_CTL, 1); 39*91f16700Schasinglulu 40*91f16700Schasinglulu mmio_write_32(DFD_V30_BASE_ADDR, (base_addr & 0xFFF00000)); 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* setup global variables for suspend and resume */ 43*91f16700Schasinglulu dfd_enabled = true; 44*91f16700Schasinglulu dfd_base_addr = base_addr; 45*91f16700Schasinglulu dfd_chain_length = chain_length; 46*91f16700Schasinglulu dfd_cache_dump = cache_dump; 47*91f16700Schasinglulu 48*91f16700Schasinglulu if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 49*91f16700Schasinglulu mmio_write_32(WDT_DEBUG_CTL, WDT_DEBUG_CTL_VAL_1); 50*91f16700Schasinglulu sync_writel(DFD_V35_ENALBE, 1); 51*91f16700Schasinglulu sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL); 52*91f16700Schasinglulu sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 53*91f16700Schasinglulu sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 54*91f16700Schasinglulu 55*91f16700Schasinglulu if (cache_dump & DFD_PARITY_ERR_TRIGGER) { 56*91f16700Schasinglulu sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL); 57*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4)); 58*91f16700Schasinglulu } 59*91f16700Schasinglulu } 60*91f16700Schasinglulu dsbsy(); 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu void dfd_resume(void) 64*91f16700Schasinglulu { 65*91f16700Schasinglulu if (dfd_enabled == true) { 66*91f16700Schasinglulu dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 67*91f16700Schasinglulu } 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, 71*91f16700Schasinglulu uint64_t arg2, uint64_t arg3) 72*91f16700Schasinglulu { 73*91f16700Schasinglulu uint64_t ret = 0L; 74*91f16700Schasinglulu 75*91f16700Schasinglulu switch (arg0) { 76*91f16700Schasinglulu case PLAT_MTK_DFD_SETUP_MAGIC: 77*91f16700Schasinglulu INFO("[%s] DFD setup call from kernel\n", __func__); 78*91f16700Schasinglulu dfd_setup(arg1, arg2, arg3); 79*91f16700Schasinglulu break; 80*91f16700Schasinglulu case PLAT_MTK_DFD_READ_MAGIC: 81*91f16700Schasinglulu /* only allow to access DFD register base + 0x200 */ 82*91f16700Schasinglulu if (arg1 <= 0x200) { 83*91f16700Schasinglulu ret = mmio_read_32(MISC1_CFG_BASE + arg1); 84*91f16700Schasinglulu } 85*91f16700Schasinglulu break; 86*91f16700Schasinglulu case PLAT_MTK_DFD_WRITE_MAGIC: 87*91f16700Schasinglulu /* only allow to access DFD register base + 0x200 */ 88*91f16700Schasinglulu if (arg1 <= 0x200) { 89*91f16700Schasinglulu sync_writel(MISC1_CFG_BASE + arg1, arg2); 90*91f16700Schasinglulu } 91*91f16700Schasinglulu break; 92*91f16700Schasinglulu default: 93*91f16700Schasinglulu ret = MTK_SIP_E_INVALID_PARAM; 94*91f16700Schasinglulu break; 95*91f16700Schasinglulu } 96*91f16700Schasinglulu 97*91f16700Schasinglulu return ret; 98*91f16700Schasinglulu } 99