1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MTK_DCM_UTILS_H 8*91f16700Schasinglulu #define MTK_DCM_UTILS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdbool.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <mtk_dcm.h> 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Base */ 16*91f16700Schasinglulu #define MP_CPUSYS_TOP_BASE 0xc538000 17*91f16700Schasinglulu #define CPCCFG_REG_BASE 0xc53a800 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* Register Definition */ 20*91f16700Schasinglulu #define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100) 21*91f16700Schasinglulu #define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0) 22*91f16700Schasinglulu #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0) 23*91f16700Schasinglulu #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) 24*91f16700Schasinglulu #define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440) 25*91f16700Schasinglulu #define MP_CPUSYS_TOP_MCSI_CFG2 (MP_CPUSYS_TOP_BASE + 0x2418) 26*91f16700Schasinglulu #define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0) 27*91f16700Schasinglulu #define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880) 28*91f16700Schasinglulu #define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c) 29*91f16700Schasinglulu #define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510) 30*91f16700Schasinglulu #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) 31*91f16700Schasinglulu 32*91f16700Schasinglulu bool dcm_mp_cpusys_top_adb_dcm_is_on(void); 33*91f16700Schasinglulu void dcm_mp_cpusys_top_adb_dcm(bool on); 34*91f16700Schasinglulu bool dcm_mp_cpusys_top_apb_dcm_is_on(void); 35*91f16700Schasinglulu void dcm_mp_cpusys_top_apb_dcm(bool on); 36*91f16700Schasinglulu bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void); 37*91f16700Schasinglulu void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on); 38*91f16700Schasinglulu bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void); 39*91f16700Schasinglulu void dcm_mp_cpusys_top_core_stall_dcm(bool on); 40*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(void); 41*91f16700Schasinglulu void dcm_mp_cpusys_top_cpubiu_dbg_cg(bool on); 42*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void); 43*91f16700Schasinglulu void dcm_mp_cpusys_top_cpubiu_dcm(bool on); 44*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void); 45*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on); 46*91f16700Schasinglulu bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void); 47*91f16700Schasinglulu void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on); 48*91f16700Schasinglulu bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void); 49*91f16700Schasinglulu void dcm_mp_cpusys_top_fcm_stall_dcm(bool on); 50*91f16700Schasinglulu bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void); 51*91f16700Schasinglulu void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on); 52*91f16700Schasinglulu bool dcm_mp_cpusys_top_misc_dcm_is_on(void); 53*91f16700Schasinglulu void dcm_mp_cpusys_top_misc_dcm(bool on); 54*91f16700Schasinglulu bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void); 55*91f16700Schasinglulu void dcm_mp_cpusys_top_mp0_qdcm(bool on); 56*91f16700Schasinglulu bool dcm_cpccfg_reg_emi_wfifo_is_on(void); 57*91f16700Schasinglulu void dcm_cpccfg_reg_emi_wfifo(bool on); 58*91f16700Schasinglulu #endif 59