1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu #include <plat_debug.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu #include <spm.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu void circular_buffer_setup(void) 15*91f16700Schasinglulu { 16*91f16700Schasinglulu /* Clear DBG_CONTROL.lastpc_disable to enable circular buffer */ 17*91f16700Schasinglulu sync_writel(CA15M_DBG_CONTROL, 18*91f16700Schasinglulu mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS)); 19*91f16700Schasinglulu } 20*91f16700Schasinglulu 21*91f16700Schasinglulu void circular_buffer_unlock(void) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu unsigned int i; 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* Disable big vproc external off (set CPU_EXT_BUCK_ISO to 0x0) */ 26*91f16700Schasinglulu sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* Release vproc apb mask (set 0x0C53_2008[1] to 0x0) */ 29*91f16700Schasinglulu sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); 30*91f16700Schasinglulu 31*91f16700Schasinglulu for (i = 1; i <= 4; ++i) 32*91f16700Schasinglulu sync_writel(MP1_CPUTOP_PWR_CON + i * 4, 33*91f16700Schasinglulu (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* Set DFD.en */ 36*91f16700Schasinglulu sync_writel(DFD_INTERNAL_CTL, 0x1); 37*91f16700Schasinglulu } 38*91f16700Schasinglulu 39*91f16700Schasinglulu void circular_buffer_lock(void) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu /* Clear DFD.en */ 42*91f16700Schasinglulu sync_writel(DFD_INTERNAL_CTL, 0x0); 43*91f16700Schasinglulu } 44*91f16700Schasinglulu 45*91f16700Schasinglulu void clear_all_on_mux(void) 46*91f16700Schasinglulu { 47*91f16700Schasinglulu sync_writel(MCU_ALL_PWR_ON_CTRL, 48*91f16700Schasinglulu mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2)); 49*91f16700Schasinglulu sync_writel(MCU_ALL_PWR_ON_CTRL, 50*91f16700Schasinglulu mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1)); 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu void l2c_parity_check_setup(void) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu /* Enable DBG_CONTROL.l2parity_en */ 56*91f16700Schasinglulu sync_writel(CA15M_DBG_CONTROL, 57*91f16700Schasinglulu mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN); 58*91f16700Schasinglulu } 59