1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEBUG_H 8*91f16700Schasinglulu #define PLATFORM_DEBUG_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define sync_writel(addr, val) \ 11*91f16700Schasinglulu do { mmio_write_32((addr), (val)); dsbsy(); } while (0) 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define MCU_BIU_BASE 0x0c530000 14*91f16700Schasinglulu #define MISC1_CFG_BASE 0xb00 15*91f16700Schasinglulu #define CA15M_CFG_BASE 0x2000 16*91f16700Schasinglulu #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00) 17*91f16700Schasinglulu #define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728) 18*91f16700Schasinglulu #define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08) 19*91f16700Schasinglulu #define VPROC_EXT_CTL 0x10006290 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define CFG_SF_CTRL 0x0c510014 22*91f16700Schasinglulu #define CFG_SF_INI 0x0c510010 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define BIT_CA15M_L2PARITY_EN (1 << 1) 25*91f16700Schasinglulu #define BIT_CA15M_LASTPC_DIS (1 << 8) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define MCU_ALL_PWR_ON_CTRL 0x0c530b58 28*91f16700Schasinglulu #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133 29*91f16700Schasinglulu #define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134 30*91f16700Schasinglulu 31*91f16700Schasinglulu extern void circular_buffer_setup(void); 32*91f16700Schasinglulu extern void l2c_parity_check_setup(void); 33*91f16700Schasinglulu extern void clear_all_on_mux(void); 34*91f16700Schasinglulu #endif /* PLATFORM_DEBUG_H */ 35