1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DCM_H 8*91f16700Schasinglulu #define PLAT_DCM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274) 11*91f16700Schasinglulu #define MP2_SYNC_DCM_MASK (0x1 << 0) 12*91f16700Schasinglulu #define MP2_SYNC_DCM_ON (0x1 << 0) 13*91f16700Schasinglulu #define MP2_SYNC_DCM_OFF (0x0 << 0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu extern uint64_t plat_dcm_mcsi_a_addr; 16*91f16700Schasinglulu extern uint32_t plat_dcm_mcsi_a_val; 17*91f16700Schasinglulu extern int plat_dcm_initiated; 18*91f16700Schasinglulu 19*91f16700Schasinglulu extern void plat_dcm_mcsi_a_backup(void); 20*91f16700Schasinglulu extern void plat_dcm_mcsi_a_restore(void); 21*91f16700Schasinglulu extern void plat_dcm_rgu_enable(void); 22*91f16700Schasinglulu extern void plat_dcm_restore_cluster_on(unsigned long mpidr); 23*91f16700Schasinglulu extern void plat_dcm_msg_handler(uint64_t x1); 24*91f16700Schasinglulu extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type); 25*91f16700Schasinglulu extern void plat_dcm_init(void); 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \ 28*91f16700Schasinglulu | STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \ 29*91f16700Schasinglulu | GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \ 30*91f16700Schasinglulu | INFRA_DCM_TYPE \ 31*91f16700Schasinglulu | DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \ 32*91f16700Schasinglulu | MCSI_DCM_TYPE) 33*91f16700Schasinglulu 34*91f16700Schasinglulu enum { 35*91f16700Schasinglulu ARMCORE_DCM_TYPE = (1U << 0), 36*91f16700Schasinglulu MCUSYS_DCM_TYPE = (1U << 1), 37*91f16700Schasinglulu INFRA_DCM_TYPE = (1U << 2), 38*91f16700Schasinglulu PERI_DCM_TYPE = (1U << 3), 39*91f16700Schasinglulu EMI_DCM_TYPE = (1U << 4), 40*91f16700Schasinglulu DRAMC_DCM_TYPE = (1U << 5), 41*91f16700Schasinglulu DDRPHY_DCM_TYPE = (1U << 6), 42*91f16700Schasinglulu STALL_DCM_TYPE = (1U << 7), 43*91f16700Schasinglulu BIG_CORE_DCM_TYPE = (1U << 8), 44*91f16700Schasinglulu GIC_SYNC_DCM_TYPE = (1U << 9), 45*91f16700Schasinglulu LAST_CORE_DCM_TYPE = (1U << 10), 46*91f16700Schasinglulu RGU_DCM_TYPE = (1U << 11), 47*91f16700Schasinglulu TOPCKG_DCM_TYPE = (1U << 12), 48*91f16700Schasinglulu LPDMA_DCM_TYPE = (1U << 13), 49*91f16700Schasinglulu MCSI_DCM_TYPE = (1U << 14), 50*91f16700Schasinglulu NR_DCM_TYPE = 15, 51*91f16700Schasinglulu }; 52*91f16700Schasinglulu 53*91f16700Schasinglulu #endif /* PLAT_DCM_H */