1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #ifndef __SSPM_H__ 7*91f16700Schasinglulu #define __SSPM_H__ 8*91f16700Schasinglulu /* These should sync with sspm.bin */ 9*91f16700Schasinglulu #define IPI_ID_PLATFORM 0 10*91f16700Schasinglulu #define IPI_ID_SUSPEND 6 11*91f16700Schasinglulu #define PINR_OFFSET_PLATFORM 0 12*91f16700Schasinglulu #define PINR_SIZE_PLATFORM 3 13*91f16700Schasinglulu #define PINR_OFFSET_SUSPEND 2 14*91f16700Schasinglulu #define PINR_SIZE_SUSPEND 8 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define MBOX0_BASE 0x10450000 17*91f16700Schasinglulu #define MBOX1_BASE 0x10460000 18*91f16700Schasinglulu #define MBOX3_BASE 0x10480000 19*91f16700Schasinglulu #define MBOX_OUT_IRQ_OFS 0x1000 20*91f16700Schasinglulu #define MBOX_IN_IRQ_OFS 0x1004 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define SHAREMBOX_OFFSET_MCDI 0 23*91f16700Schasinglulu #define SHAREMBOX_SIZE_MCDI 20 24*91f16700Schasinglulu #define SHAREMBOX_OFFSET_SUSPEND 26 25*91f16700Schasinglulu #define SHAREMBOX_SIZE_SUSPEND 6 26*91f16700Schasinglulu 27*91f16700Schasinglulu int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len); 28*91f16700Schasinglulu int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len); 29*91f16700Schasinglulu int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data); 30*91f16700Schasinglulu int sspm_ipi_recv_non_blocking(uint32_t slot, uint32_t *data, uint32_t len); 31*91f16700Schasinglulu int sspm_alive_show(void); 32*91f16700Schasinglulu #endif /* __SSPM_H__ */ 33