1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SPM_H 8*91f16700Schasinglulu #define SPM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /************************************** 11*91f16700Schasinglulu * Define and Declare 12*91f16700Schasinglulu **************************************/ 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 15*91f16700Schasinglulu #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 16*91f16700Schasinglulu #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 17*91f16700Schasinglulu #define SPM_CLK_CON (SPM_BASE + 0x00C) 18*91f16700Schasinglulu #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 19*91f16700Schasinglulu #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 20*91f16700Schasinglulu #define PCM_CON0 (SPM_BASE + 0x018) 21*91f16700Schasinglulu #define PCM_CON1 (SPM_BASE + 0x01C) 22*91f16700Schasinglulu #define PCM_IM_PTR (SPM_BASE + 0x020) 23*91f16700Schasinglulu #define PCM_IM_LEN (SPM_BASE + 0x024) 24*91f16700Schasinglulu #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 25*91f16700Schasinglulu #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 26*91f16700Schasinglulu #define PCM_TIMER_VAL (SPM_BASE + 0x030) 27*91f16700Schasinglulu #define PCM_WDT_VAL (SPM_BASE + 0x034) 28*91f16700Schasinglulu #define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) 29*91f16700Schasinglulu #define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) 30*91f16700Schasinglulu #define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) 31*91f16700Schasinglulu #define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) 32*91f16700Schasinglulu #define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) 33*91f16700Schasinglulu #define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) 34*91f16700Schasinglulu #define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) 35*91f16700Schasinglulu #define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) 36*91f16700Schasinglulu #define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) 37*91f16700Schasinglulu #define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) 38*91f16700Schasinglulu #define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) 39*91f16700Schasinglulu #define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) 40*91f16700Schasinglulu #define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) 41*91f16700Schasinglulu #define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) 42*91f16700Schasinglulu #define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) 43*91f16700Schasinglulu #define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) 44*91f16700Schasinglulu #define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) 45*91f16700Schasinglulu #define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) 46*91f16700Schasinglulu #define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) 47*91f16700Schasinglulu #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) 48*91f16700Schasinglulu #define SPM_SWINT (SPM_BASE + 0x08C) 49*91f16700Schasinglulu #define SPM_SWINT_SET (SPM_BASE + 0x090) 50*91f16700Schasinglulu #define SPM_SWINT_CLR (SPM_BASE + 0x094) 51*91f16700Schasinglulu #define SPM_SCP_MAILBOX (SPM_BASE + 0x098) 52*91f16700Schasinglulu #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) 53*91f16700Schasinglulu #define SPM_TWAM_CON (SPM_BASE + 0x0A0) 54*91f16700Schasinglulu #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) 55*91f16700Schasinglulu #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) 56*91f16700Schasinglulu #define SPM_SCP_IRQ (SPM_BASE + 0x0AC) 57*91f16700Schasinglulu #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) 58*91f16700Schasinglulu #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) 59*91f16700Schasinglulu #define SPM_SRC_REQ (SPM_BASE + 0x0B8) 60*91f16700Schasinglulu #define SPM_SRC_MASK (SPM_BASE + 0x0BC) 61*91f16700Schasinglulu #define SPM_SRC2_MASK (SPM_BASE + 0x0C0) 62*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) 63*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) 64*91f16700Schasinglulu #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC) 65*91f16700Schasinglulu #define SCP_CLK_CON (SPM_BASE + 0x0D0) 66*91f16700Schasinglulu #define PCM_DEBUG_CON (SPM_BASE + 0x0D4) 67*91f16700Schasinglulu #define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8) 68*91f16700Schasinglulu #define AHB_BUS_CON (SPM_BASE + 0x0DC) 69*91f16700Schasinglulu #define SPM_SRC3_MASK (SPM_BASE + 0x0E0) 70*91f16700Schasinglulu #define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4) 71*91f16700Schasinglulu #define SSPM_CLK_CON (SPM_BASE + 0x0E8) 72*91f16700Schasinglulu #define PCM_REG0_DATA (SPM_BASE + 0x100) 73*91f16700Schasinglulu #define PCM_REG1_DATA (SPM_BASE + 0x104) 74*91f16700Schasinglulu #define PCM_REG2_DATA (SPM_BASE + 0x108) 75*91f16700Schasinglulu #define PCM_REG3_DATA (SPM_BASE + 0x10C) 76*91f16700Schasinglulu #define PCM_REG4_DATA (SPM_BASE + 0x110) 77*91f16700Schasinglulu #define PCM_REG5_DATA (SPM_BASE + 0x114) 78*91f16700Schasinglulu #define PCM_REG6_DATA (SPM_BASE + 0x118) 79*91f16700Schasinglulu #define PCM_REG7_DATA (SPM_BASE + 0x11C) 80*91f16700Schasinglulu #define PCM_REG8_DATA (SPM_BASE + 0x120) 81*91f16700Schasinglulu #define PCM_REG9_DATA (SPM_BASE + 0x124) 82*91f16700Schasinglulu #define PCM_REG10_DATA (SPM_BASE + 0x128) 83*91f16700Schasinglulu #define PCM_REG11_DATA (SPM_BASE + 0x12C) 84*91f16700Schasinglulu #define PCM_REG12_DATA (SPM_BASE + 0x130) 85*91f16700Schasinglulu #define PCM_REG13_DATA (SPM_BASE + 0x134) 86*91f16700Schasinglulu #define PCM_REG14_DATA (SPM_BASE + 0x138) 87*91f16700Schasinglulu #define PCM_REG15_DATA (SPM_BASE + 0x13C) 88*91f16700Schasinglulu #define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) 89*91f16700Schasinglulu #define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) 90*91f16700Schasinglulu #define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) 91*91f16700Schasinglulu #define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) 92*91f16700Schasinglulu #define PCM_TIMER_OUT (SPM_BASE + 0x150) 93*91f16700Schasinglulu #define PCM_WDT_OUT (SPM_BASE + 0x154) 94*91f16700Schasinglulu #define SPM_IRQ_STA (SPM_BASE + 0x158) 95*91f16700Schasinglulu #define SPM_WAKEUP_STA (SPM_BASE + 0x15C) 96*91f16700Schasinglulu #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) 97*91f16700Schasinglulu #define SPM_WAKEUP_MISC (SPM_BASE + 0x164) 98*91f16700Schasinglulu #define BUS_PROTECT_RDY (SPM_BASE + 0x168) 99*91f16700Schasinglulu #define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) 100*91f16700Schasinglulu #define SUBSYS_IDLE_STA (SPM_BASE + 0x170) 101*91f16700Schasinglulu #define CPU_IDLE_STA (SPM_BASE + 0x174) 102*91f16700Schasinglulu #define PCM_FSM_STA (SPM_BASE + 0x178) 103*91f16700Schasinglulu #define SRC_REQ_STA (SPM_BASE + 0x17C) 104*91f16700Schasinglulu #define PWR_STATUS (SPM_BASE + 0x180) 105*91f16700Schasinglulu #define PWR_STATUS_2ND (SPM_BASE + 0x184) 106*91f16700Schasinglulu #define CPU_PWR_STATUS (SPM_BASE + 0x188) 107*91f16700Schasinglulu #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) 108*91f16700Schasinglulu #define MISC_STA (SPM_BASE + 0x190) 109*91f16700Schasinglulu #define SPM_SRC_RDY_STA (SPM_BASE + 0x194) 110*91f16700Schasinglulu #define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) 111*91f16700Schasinglulu #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) 112*91f16700Schasinglulu #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) 113*91f16700Schasinglulu #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) 114*91f16700Schasinglulu #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) 115*91f16700Schasinglulu #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) 116*91f16700Schasinglulu #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) 117*91f16700Schasinglulu #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) 118*91f16700Schasinglulu #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) 119*91f16700Schasinglulu #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) 120*91f16700Schasinglulu #define SPM_DVFS_STA (SPM_BASE + 0x1C8) 121*91f16700Schasinglulu #define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC) 122*91f16700Schasinglulu #define SRC_DDREN_STA (SPM_BASE + 0x1E0) 123*91f16700Schasinglulu #define MCU_PWR_CON (SPM_BASE + 0x200) 124*91f16700Schasinglulu #define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) 125*91f16700Schasinglulu #define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) 126*91f16700Schasinglulu #define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) 127*91f16700Schasinglulu #define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) 128*91f16700Schasinglulu #define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) 129*91f16700Schasinglulu #define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) 130*91f16700Schasinglulu #define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) 131*91f16700Schasinglulu #define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) 132*91f16700Schasinglulu #define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) 133*91f16700Schasinglulu #define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) 134*91f16700Schasinglulu #define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) 135*91f16700Schasinglulu #define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) 136*91f16700Schasinglulu #define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) 137*91f16700Schasinglulu #define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) 138*91f16700Schasinglulu #define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) 139*91f16700Schasinglulu #define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) 140*91f16700Schasinglulu #define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) 141*91f16700Schasinglulu #define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) 142*91f16700Schasinglulu #define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) 143*91f16700Schasinglulu #define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) 144*91f16700Schasinglulu #define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) 145*91f16700Schasinglulu #define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) 146*91f16700Schasinglulu #define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) 147*91f16700Schasinglulu #define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) 148*91f16700Schasinglulu #define BYPASS_SPMC (SPM_BASE + 0x2B4) 149*91f16700Schasinglulu #define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) 150*91f16700Schasinglulu #define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) 151*91f16700Schasinglulu #define SPMC_IN_RET (SPM_BASE + 0x2C0) 152*91f16700Schasinglulu #define VDE_PWR_CON (SPM_BASE + 0x300) 153*91f16700Schasinglulu #define VEN_PWR_CON (SPM_BASE + 0x304) 154*91f16700Schasinglulu #define ISP_PWR_CON (SPM_BASE + 0x308) 155*91f16700Schasinglulu #define DIS_PWR_CON (SPM_BASE + 0x30C) 156*91f16700Schasinglulu #define MFG_CORE1_PWR_CON (SPM_BASE + 0x310) 157*91f16700Schasinglulu #define AUDIO_PWR_CON (SPM_BASE + 0x314) 158*91f16700Schasinglulu #define IFR_PWR_CON (SPM_BASE + 0x318) 159*91f16700Schasinglulu #define DPY_PWR_CON (SPM_BASE + 0x31C) 160*91f16700Schasinglulu #define MD1_PWR_CON (SPM_BASE + 0x320) 161*91f16700Schasinglulu #define VPU_TOP_PWR_CON (SPM_BASE + 0x324) 162*91f16700Schasinglulu #define CONN_PWR_CON (SPM_BASE + 0x32C) 163*91f16700Schasinglulu #define VPU_CORE2_PWR_CON (SPM_BASE + 0x330) 164*91f16700Schasinglulu #define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) 165*91f16700Schasinglulu #define MFG_PWR_CON (SPM_BASE + 0x338) 166*91f16700Schasinglulu #define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C) 167*91f16700Schasinglulu #define VPU_CORE1_PWR_CON (SPM_BASE + 0x340) 168*91f16700Schasinglulu #define CAM_PWR_CON (SPM_BASE + 0x344) 169*91f16700Schasinglulu #define MFG_2D_PWR_CON (SPM_BASE + 0x348) 170*91f16700Schasinglulu #define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C) 171*91f16700Schasinglulu #define SYSRAM_CON (SPM_BASE + 0x350) 172*91f16700Schasinglulu #define SYSROM_CON (SPM_BASE + 0x354) 173*91f16700Schasinglulu #define SSPM_SRAM_CON (SPM_BASE + 0x358) 174*91f16700Schasinglulu #define SCP_SRAM_CON (SPM_BASE + 0x35C) 175*91f16700Schasinglulu #define UFS_SRAM_CON (SPM_BASE + 0x36C) 176*91f16700Schasinglulu #define DUMMY_SRAM_CON (SPM_BASE + 0x380) 177*91f16700Schasinglulu #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390) 178*91f16700Schasinglulu #define MD_SRAM_ISO_CON (SPM_BASE + 0x394) 179*91f16700Schasinglulu #define MD_EXTRA_PWR_CON (SPM_BASE + 0x398) 180*91f16700Schasinglulu #define EXT_BUCK_CON (SPM_BASE + 0x3A0) 181*91f16700Schasinglulu #define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0) 182*91f16700Schasinglulu #define SPM_DVFS_CON (SPM_BASE + 0x400) 183*91f16700Schasinglulu #define SPM_MDBSI_CON (SPM_BASE + 0x404) 184*91f16700Schasinglulu #define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) 185*91f16700Schasinglulu #define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) 186*91f16700Schasinglulu #define SPM_BSI_GEN (SPM_BASE + 0x410) 187*91f16700Schasinglulu #define SPM_BSI_EN_SR (SPM_BASE + 0x414) 188*91f16700Schasinglulu #define SPM_BSI_CLK_SR (SPM_BASE + 0x418) 189*91f16700Schasinglulu #define SPM_BSI_D0_SR (SPM_BASE + 0x41C) 190*91f16700Schasinglulu #define SPM_BSI_D1_SR (SPM_BASE + 0x420) 191*91f16700Schasinglulu #define SPM_BSI_D2_SR (SPM_BASE + 0x424) 192*91f16700Schasinglulu #define SPM_AP_SEMA (SPM_BASE + 0x428) 193*91f16700Schasinglulu #define SPM_SPM_SEMA (SPM_BASE + 0x42C) 194*91f16700Schasinglulu #define AP_MDSRC_REQ (SPM_BASE + 0x430) 195*91f16700Schasinglulu #define SPM2MD_DVFS_CON (SPM_BASE + 0x438) 196*91f16700Schasinglulu #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) 197*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) 198*91f16700Schasinglulu #define DPY_LP_CON (SPM_BASE + 0x444) 199*91f16700Schasinglulu #define CPU_DVFS_REQ (SPM_BASE + 0x448) 200*91f16700Schasinglulu #define SPM_PLL_CON (SPM_BASE + 0x44C) 201*91f16700Schasinglulu #define SPM_EMI_BW_MODE (SPM_BASE + 0x450) 202*91f16700Schasinglulu #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) 203*91f16700Schasinglulu #define ULPOSC_CON (SPM_BASE + 0x458) 204*91f16700Schasinglulu #define SPM2MM_CON (SPM_BASE + 0x45C) 205*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) 206*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) 207*91f16700Schasinglulu #define SPM_S1_MODE_CH (SPM_BASE + 0x468) 208*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C) 209*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) 210*91f16700Schasinglulu #define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) 211*91f16700Schasinglulu #define DRAMC_DMYRD_CON (SPM_BASE + 0x478) 212*91f16700Schasinglulu #define SPM_DRS_CON (SPM_BASE + 0x47C) 213*91f16700Schasinglulu #define SPM_SEMA_M0 (SPM_BASE + 0x480) 214*91f16700Schasinglulu #define SPM_SEMA_M1 (SPM_BASE + 0x484) 215*91f16700Schasinglulu #define SPM_SEMA_M2 (SPM_BASE + 0x488) 216*91f16700Schasinglulu #define SPM_SEMA_M3 (SPM_BASE + 0x48C) 217*91f16700Schasinglulu #define SPM_SEMA_M4 (SPM_BASE + 0x490) 218*91f16700Schasinglulu #define SPM_SEMA_M5 (SPM_BASE + 0x494) 219*91f16700Schasinglulu #define SPM_SEMA_M6 (SPM_BASE + 0x498) 220*91f16700Schasinglulu #define SPM_SEMA_M7 (SPM_BASE + 0x49C) 221*91f16700Schasinglulu #define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0) 222*91f16700Schasinglulu #define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4) 223*91f16700Schasinglulu #define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) 224*91f16700Schasinglulu #define SRAM_DREQ_CON (SPM_BASE + 0x4B0) 225*91f16700Schasinglulu #define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) 226*91f16700Schasinglulu #define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) 227*91f16700Schasinglulu #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC) 228*91f16700Schasinglulu #define SPM_SSPM_IRQ (SPM_BASE + 0x4C0) 229*91f16700Schasinglulu #define SPM2PMCU_INT (SPM_BASE + 0x4C4) 230*91f16700Schasinglulu #define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8) 231*91f16700Schasinglulu #define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC) 232*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0) 233*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4) 234*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8) 235*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC) 236*91f16700Schasinglulu #define PMCU2SPM_INT (SPM_BASE + 0x4E0) 237*91f16700Schasinglulu #define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4) 238*91f16700Schasinglulu #define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8) 239*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC) 240*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0) 241*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4) 242*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8) 243*91f16700Schasinglulu #define PMCU2SPM_CFG (SPM_BASE + 0x4FC) 244*91f16700Schasinglulu #define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) 245*91f16700Schasinglulu #define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) 246*91f16700Schasinglulu #define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) 247*91f16700Schasinglulu #define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) 248*91f16700Schasinglulu #define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) 249*91f16700Schasinglulu #define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) 250*91f16700Schasinglulu #define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) 251*91f16700Schasinglulu #define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) 252*91f16700Schasinglulu #define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) 253*91f16700Schasinglulu #define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) 254*91f16700Schasinglulu #define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) 255*91f16700Schasinglulu #define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) 256*91f16700Schasinglulu #define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) 257*91f16700Schasinglulu #define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) 258*91f16700Schasinglulu #define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) 259*91f16700Schasinglulu #define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) 260*91f16700Schasinglulu #define MP0_L2CFLUSH (SPM_BASE + 0x554) 261*91f16700Schasinglulu #define MP1_L2CFLUSH (SPM_BASE + 0x558) 262*91f16700Schasinglulu #define CPU_PTPOD2_CON (SPM_BASE + 0x560) 263*91f16700Schasinglulu #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) 264*91f16700Schasinglulu #define ROOT_CORE_ADDR (SPM_BASE + 0x574) 265*91f16700Schasinglulu #define CPU_SPARE_CON (SPM_BASE + 0x580) 266*91f16700Schasinglulu #define CPU_SPARE_CON_SET (SPM_BASE + 0x584) 267*91f16700Schasinglulu #define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) 268*91f16700Schasinglulu #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0) 269*91f16700Schasinglulu #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4) 270*91f16700Schasinglulu #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8) 271*91f16700Schasinglulu #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC) 272*91f16700Schasinglulu #define SW2SPM_INT (SPM_BASE + 0x5E0) 273*91f16700Schasinglulu #define SW2SPM_INT_SET (SPM_BASE + 0x5E4) 274*91f16700Schasinglulu #define SW2SPM_INT_CLR (SPM_BASE + 0x5E8) 275*91f16700Schasinglulu #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC) 276*91f16700Schasinglulu #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0) 277*91f16700Schasinglulu #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4) 278*91f16700Schasinglulu #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8) 279*91f16700Schasinglulu #define SW2SPM_CFG (SPM_BASE + 0x5FC) 280*91f16700Schasinglulu #define SPM_SW_FLAG (SPM_BASE + 0x600) 281*91f16700Schasinglulu #define SPM_SW_DEBUG (SPM_BASE + 0x604) 282*91f16700Schasinglulu #define SPM_SW_RSV_0 (SPM_BASE + 0x608) 283*91f16700Schasinglulu #define SPM_SW_RSV_1 (SPM_BASE + 0x60C) 284*91f16700Schasinglulu #define SPM_SW_RSV_2 (SPM_BASE + 0x610) 285*91f16700Schasinglulu #define SPM_SW_RSV_3 (SPM_BASE + 0x614) 286*91f16700Schasinglulu #define SPM_SW_RSV_4 (SPM_BASE + 0x618) 287*91f16700Schasinglulu #define SPM_SW_RSV_5 (SPM_BASE + 0x61C) 288*91f16700Schasinglulu #define SPM_RSV_CON (SPM_BASE + 0x620) 289*91f16700Schasinglulu #define SPM_RSV_STA (SPM_BASE + 0x624) 290*91f16700Schasinglulu #define SPM_RSV_CON1 (SPM_BASE + 0x628) 291*91f16700Schasinglulu #define SPM_RSV_STA1 (SPM_BASE + 0x62C) 292*91f16700Schasinglulu #define SPM_PASR_DPD_0 (SPM_BASE + 0x630) 293*91f16700Schasinglulu #define SPM_PASR_DPD_1 (SPM_BASE + 0x634) 294*91f16700Schasinglulu #define SPM_PASR_DPD_2 (SPM_BASE + 0x638) 295*91f16700Schasinglulu #define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) 296*91f16700Schasinglulu #define SPM_SPARE_CON (SPM_BASE + 0x640) 297*91f16700Schasinglulu #define SPM_SPARE_CON_SET (SPM_BASE + 0x644) 298*91f16700Schasinglulu #define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) 299*91f16700Schasinglulu #define SPM_SW_RSV_6 (SPM_BASE + 0x64C) 300*91f16700Schasinglulu #define SPM_SW_RSV_7 (SPM_BASE + 0x650) 301*91f16700Schasinglulu #define SPM_SW_RSV_8 (SPM_BASE + 0x654) 302*91f16700Schasinglulu #define SPM_SW_RSV_9 (SPM_BASE + 0x658) 303*91f16700Schasinglulu #define SPM_SW_RSV_10 (SPM_BASE + 0x65C) 304*91f16700Schasinglulu #define SPM_SW_RSV_18 (SPM_BASE + 0x67C) 305*91f16700Schasinglulu #define SPM_SW_RSV_19 (SPM_BASE + 0x680) 306*91f16700Schasinglulu #define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690) 307*91f16700Schasinglulu #define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694) 308*91f16700Schasinglulu #define DVFSRC_EVENT_SEL (SPM_BASE + 0x698) 309*91f16700Schasinglulu #define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C) 310*91f16700Schasinglulu #define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0) 311*91f16700Schasinglulu #define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4) 312*91f16700Schasinglulu #define DVFS_ABORT_STA (SPM_BASE + 0x6A8) 313*91f16700Schasinglulu #define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC) 314*91f16700Schasinglulu #define SPM_DFS_LEVEL (SPM_BASE + 0x6B0) 315*91f16700Schasinglulu #define SPM_DVS_LEVEL (SPM_BASE + 0x6B4) 316*91f16700Schasinglulu #define SPM_DVFS_MISC (SPM_BASE + 0x6B8) 317*91f16700Schasinglulu #define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0) 318*91f16700Schasinglulu #define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4) 319*91f16700Schasinglulu #define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8) 320*91f16700Schasinglulu #define SPARE_ACK_STA (SPM_BASE + 0x6F0) 321*91f16700Schasinglulu #define SPARE_ACK_MASK (SPM_BASE + 0x6F4) 322*91f16700Schasinglulu #define SPM_DVFS_CON1 (SPM_BASE + 0x700) 323*91f16700Schasinglulu #define SPM_DVFS_CON1_STA (SPM_BASE + 0x704) 324*91f16700Schasinglulu #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 325*91f16700Schasinglulu #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 326*91f16700Schasinglulu #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 327*91f16700Schasinglulu #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 328*91f16700Schasinglulu #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 329*91f16700Schasinglulu #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 330*91f16700Schasinglulu #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 331*91f16700Schasinglulu #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 332*91f16700Schasinglulu #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 333*91f16700Schasinglulu #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 334*91f16700Schasinglulu #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 335*91f16700Schasinglulu #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 336*91f16700Schasinglulu #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 337*91f16700Schasinglulu #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 338*91f16700Schasinglulu #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 339*91f16700Schasinglulu #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 340*91f16700Schasinglulu #define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780) 341*91f16700Schasinglulu #define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784) 342*91f16700Schasinglulu #define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788) 343*91f16700Schasinglulu #define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C) 344*91f16700Schasinglulu #define SPARE_ACK_IN_FIX (SPM_BASE + 0x790) 345*91f16700Schasinglulu #define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794) 346*91f16700Schasinglulu #define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798) 347*91f16700Schasinglulu #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 348*91f16700Schasinglulu #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 349*91f16700Schasinglulu #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 350*91f16700Schasinglulu #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 351*91f16700Schasinglulu #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 352*91f16700Schasinglulu #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 353*91f16700Schasinglulu #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 354*91f16700Schasinglulu #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 355*91f16700Schasinglulu #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 356*91f16700Schasinglulu #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 357*91f16700Schasinglulu #define WDT_LATCH_SPARE0 (SPM_BASE + 0x828) 358*91f16700Schasinglulu #define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C) 359*91f16700Schasinglulu #define WDT_LATCH_SPARE2 (SPM_BASE + 0x830) 360*91f16700Schasinglulu #define WDT_LATCH_SPARE3 (SPM_BASE + 0x834) 361*91f16700Schasinglulu #define PCM_WDT_LATCH_10 (SPM_BASE + 0x838) 362*91f16700Schasinglulu #define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C) 363*91f16700Schasinglulu #define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840) 364*91f16700Schasinglulu #define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844) 365*91f16700Schasinglulu #define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848) 366*91f16700Schasinglulu #define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C) 367*91f16700Schasinglulu #define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850) 368*91f16700Schasinglulu #define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854) 369*91f16700Schasinglulu #define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858) 370*91f16700Schasinglulu #define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C) 371*91f16700Schasinglulu #define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860) 372*91f16700Schasinglulu #define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864) 373*91f16700Schasinglulu #define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868) 374*91f16700Schasinglulu #define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C) 375*91f16700Schasinglulu #define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870) 376*91f16700Schasinglulu #define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874) 377*91f16700Schasinglulu #define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878) 378*91f16700Schasinglulu #define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C) 379*91f16700Schasinglulu #define DCHA_LATCH_RSV0 (SPM_BASE + 0x880) 380*91f16700Schasinglulu #define DCHB_LATCH_RSV0 (SPM_BASE + 0x884) 381*91f16700Schasinglulu #define PCM_WDT_LATCH_12 (SPM_BASE + 0x888) 382*91f16700Schasinglulu #define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C) 383*91f16700Schasinglulu #define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0) 384*91f16700Schasinglulu #define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4) 385*91f16700Schasinglulu #define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8) 386*91f16700Schasinglulu #define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC) 387*91f16700Schasinglulu #define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0) 388*91f16700Schasinglulu #define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4) 389*91f16700Schasinglulu #define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8) 390*91f16700Schasinglulu #define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC) 391*91f16700Schasinglulu #define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0) 392*91f16700Schasinglulu #define SPM_ACK_CHK_CON (SPM_BASE + 0x900) 393*91f16700Schasinglulu #define SPM_ACK_CHK_PC (SPM_BASE + 0x904) 394*91f16700Schasinglulu #define SPM_ACK_CHK_SEL (SPM_BASE + 0x908) 395*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C) 396*91f16700Schasinglulu #define SPM_ACK_CHK_STA (SPM_BASE + 0x910) 397*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914) 398*91f16700Schasinglulu #define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920) 399*91f16700Schasinglulu #define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924) 400*91f16700Schasinglulu #define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928) 401*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C) 402*91f16700Schasinglulu #define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930) 403*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934) 404*91f16700Schasinglulu #define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940) 405*91f16700Schasinglulu #define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944) 406*91f16700Schasinglulu #define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948) 407*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C) 408*91f16700Schasinglulu #define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950) 409*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954) 410*91f16700Schasinglulu #define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960) 411*91f16700Schasinglulu #define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964) 412*91f16700Schasinglulu #define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968) 413*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C) 414*91f16700Schasinglulu #define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970) 415*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974) 416*91f16700Schasinglulu 417*91f16700Schasinglulu /* POWERON_CONFIG_EN (0x10006000+0x000) */ 418*91f16700Schasinglulu #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 419*91f16700Schasinglulu #define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ 420*91f16700Schasinglulu #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 421*91f16700Schasinglulu /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ 422*91f16700Schasinglulu #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 423*91f16700Schasinglulu /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ 424*91f16700Schasinglulu #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 425*91f16700Schasinglulu /* SPM_CLK_CON (0x10006000+0x00C) */ 426*91f16700Schasinglulu #define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ 427*91f16700Schasinglulu #define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ 428*91f16700Schasinglulu #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 429*91f16700Schasinglulu #define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 430*91f16700Schasinglulu #define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 431*91f16700Schasinglulu #define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ 432*91f16700Schasinglulu #define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ 433*91f16700Schasinglulu #define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 434*91f16700Schasinglulu #define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 435*91f16700Schasinglulu #define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ 436*91f16700Schasinglulu #define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ 437*91f16700Schasinglulu #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 438*91f16700Schasinglulu #define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ 439*91f16700Schasinglulu #define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ 440*91f16700Schasinglulu /* SPM_CLK_SETTLE (0x10006000+0x010) */ 441*91f16700Schasinglulu #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 442*91f16700Schasinglulu /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ 443*91f16700Schasinglulu #define WFI_OP_LSB (1U << 0) /* 1b */ 444*91f16700Schasinglulu #define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ 445*91f16700Schasinglulu #define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 446*91f16700Schasinglulu #define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 447*91f16700Schasinglulu #define MM_MASK_B_LSB (1U << 16) /* 2b */ 448*91f16700Schasinglulu #define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ 449*91f16700Schasinglulu #define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ 450*91f16700Schasinglulu #define MD_MASK_B_LSB (1U << 20) /* 2b */ 451*91f16700Schasinglulu #define SSPM_MASK_B_LSB (1U << 22) /* 1b */ 452*91f16700Schasinglulu #define SCP_MASK_B_LSB (1U << 23) /* 1b */ 453*91f16700Schasinglulu #define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ 454*91f16700Schasinglulu #define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 455*91f16700Schasinglulu #define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 456*91f16700Schasinglulu #define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ 457*91f16700Schasinglulu #define CONN_MASK_B_LSB (1U << 28) /* 1b */ 458*91f16700Schasinglulu #define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 459*91f16700Schasinglulu /* PCM_CON0 (0x10006000+0x018) */ 460*91f16700Schasinglulu #define PCM_KICK_L_LSB (1U << 0) /* 1b */ 461*91f16700Schasinglulu #define IM_KICK_L_LSB (1U << 1) /* 1b */ 462*91f16700Schasinglulu #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 463*91f16700Schasinglulu #define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 464*91f16700Schasinglulu #define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ 465*91f16700Schasinglulu #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 466*91f16700Schasinglulu #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 467*91f16700Schasinglulu /* PCM_CON1 (0x10006000+0x01C) */ 468*91f16700Schasinglulu #define IM_SLAVE_LSB (1U << 0) /* 1b */ 469*91f16700Schasinglulu #define IM_SLEEP_LSB (1U << 1) /* 1b */ 470*91f16700Schasinglulu #define MIF_APBEN_LSB (1U << 3) /* 1b */ 471*91f16700Schasinglulu #define IM_PDN_LSB (1U << 4) /* 1b */ 472*91f16700Schasinglulu #define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 473*91f16700Schasinglulu #define IM_NONRP_EN_LSB (1U << 6) /* 1b */ 474*91f16700Schasinglulu #define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 475*91f16700Schasinglulu #define PCM_WDT_EN_LSB (1U << 8) /* 1b */ 476*91f16700Schasinglulu #define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ 477*91f16700Schasinglulu #define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 478*91f16700Schasinglulu #define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 479*91f16700Schasinglulu #define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 480*91f16700Schasinglulu #define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 481*91f16700Schasinglulu #define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 482*91f16700Schasinglulu #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 483*91f16700Schasinglulu /* PCM_IM_PTR (0x10006000+0x020) */ 484*91f16700Schasinglulu #define PCM_IM_PTR_LSB (1U << 0) /* 32b */ 485*91f16700Schasinglulu /* PCM_IM_LEN (0x10006000+0x024) */ 486*91f16700Schasinglulu #define PCM_IM_LEN_LSB (1U << 0) /* 13b */ 487*91f16700Schasinglulu /* PCM_REG_DATA_INI (0x10006000+0x028) */ 488*91f16700Schasinglulu #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 489*91f16700Schasinglulu /* PCM_PWR_IO_EN (0x10006000+0x02C) */ 490*91f16700Schasinglulu #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 491*91f16700Schasinglulu #define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 492*91f16700Schasinglulu /* PCM_TIMER_VAL (0x10006000+0x030) */ 493*91f16700Schasinglulu #define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 494*91f16700Schasinglulu /* PCM_WDT_VAL (0x10006000+0x034) */ 495*91f16700Schasinglulu #define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 496*91f16700Schasinglulu /* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ 497*91f16700Schasinglulu #define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ 498*91f16700Schasinglulu #define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ 499*91f16700Schasinglulu #define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ 500*91f16700Schasinglulu /* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ 501*91f16700Schasinglulu #define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ 502*91f16700Schasinglulu /* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ 503*91f16700Schasinglulu #define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ 504*91f16700Schasinglulu #define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ 505*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ 506*91f16700Schasinglulu #define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ 507*91f16700Schasinglulu /* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ 508*91f16700Schasinglulu #define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ 509*91f16700Schasinglulu #define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ 510*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ 511*91f16700Schasinglulu #define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ 512*91f16700Schasinglulu /* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ 513*91f16700Schasinglulu #define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ 514*91f16700Schasinglulu #define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ 515*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ 516*91f16700Schasinglulu #define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ 517*91f16700Schasinglulu /* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ 518*91f16700Schasinglulu #define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ 519*91f16700Schasinglulu #define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ 520*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ 521*91f16700Schasinglulu #define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ 522*91f16700Schasinglulu /* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ 523*91f16700Schasinglulu #define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ 524*91f16700Schasinglulu #define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ 525*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ 526*91f16700Schasinglulu #define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ 527*91f16700Schasinglulu /* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ 528*91f16700Schasinglulu #define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ 529*91f16700Schasinglulu #define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ 530*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ 531*91f16700Schasinglulu #define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ 532*91f16700Schasinglulu /* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ 533*91f16700Schasinglulu #define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ 534*91f16700Schasinglulu #define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ 535*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ 536*91f16700Schasinglulu #define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ 537*91f16700Schasinglulu /* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ 538*91f16700Schasinglulu #define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ 539*91f16700Schasinglulu #define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ 540*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ 541*91f16700Schasinglulu #define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ 542*91f16700Schasinglulu /* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ 543*91f16700Schasinglulu #define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ 544*91f16700Schasinglulu #define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ 545*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ 546*91f16700Schasinglulu #define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ 547*91f16700Schasinglulu /* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ 548*91f16700Schasinglulu #define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ 549*91f16700Schasinglulu #define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ 550*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ 551*91f16700Schasinglulu #define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ 552*91f16700Schasinglulu /* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ 553*91f16700Schasinglulu #define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ 554*91f16700Schasinglulu #define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ 555*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ 556*91f16700Schasinglulu #define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ 557*91f16700Schasinglulu /* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ 558*91f16700Schasinglulu #define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ 559*91f16700Schasinglulu #define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ 560*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ 561*91f16700Schasinglulu #define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ 562*91f16700Schasinglulu /* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ 563*91f16700Schasinglulu #define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ 564*91f16700Schasinglulu #define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ 565*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ 566*91f16700Schasinglulu #define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ 567*91f16700Schasinglulu /* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ 568*91f16700Schasinglulu #define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ 569*91f16700Schasinglulu #define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ 570*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ 571*91f16700Schasinglulu #define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ 572*91f16700Schasinglulu /* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ 573*91f16700Schasinglulu #define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ 574*91f16700Schasinglulu #define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ 575*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ 576*91f16700Schasinglulu #define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ 577*91f16700Schasinglulu /* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ 578*91f16700Schasinglulu #define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ 579*91f16700Schasinglulu #define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ 580*91f16700Schasinglulu #define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ 581*91f16700Schasinglulu #define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ 582*91f16700Schasinglulu /* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ 583*91f16700Schasinglulu #define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ 584*91f16700Schasinglulu /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ 585*91f16700Schasinglulu #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 586*91f16700Schasinglulu /* SPM_SWINT (0x10006000+0x08C) */ 587*91f16700Schasinglulu #define SPM_SWINT_LSB (1U << 0) /* 10b */ 588*91f16700Schasinglulu /* SPM_SWINT_SET (0x10006000+0x090) */ 589*91f16700Schasinglulu #define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ 590*91f16700Schasinglulu /* SPM_SWINT_CLR (0x10006000+0x094) */ 591*91f16700Schasinglulu #define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ 592*91f16700Schasinglulu /* SPM_SCP_MAILBOX (0x10006000+0x098) */ 593*91f16700Schasinglulu #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 594*91f16700Schasinglulu /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ 595*91f16700Schasinglulu #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 596*91f16700Schasinglulu /* SPM_TWAM_CON (0x10006000+0x0A0) */ 597*91f16700Schasinglulu #define TWAM_ENABLE_LSB (1U << 0) /* 1b */ 598*91f16700Schasinglulu #define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ 599*91f16700Schasinglulu #define TWAM_SW_RST_LSB (1U << 2) /* 1b */ 600*91f16700Schasinglulu #define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ 601*91f16700Schasinglulu #define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ 602*91f16700Schasinglulu #define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ 603*91f16700Schasinglulu #define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ 604*91f16700Schasinglulu #define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ 605*91f16700Schasinglulu #define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ 606*91f16700Schasinglulu #define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ 607*91f16700Schasinglulu #define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ 608*91f16700Schasinglulu /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ 609*91f16700Schasinglulu #define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 610*91f16700Schasinglulu /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ 611*91f16700Schasinglulu #define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ 612*91f16700Schasinglulu /* SPM_SCP_IRQ (0x10006000+0x0AC) */ 613*91f16700Schasinglulu #define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ 614*91f16700Schasinglulu #define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ 615*91f16700Schasinglulu /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ 616*91f16700Schasinglulu #define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ 617*91f16700Schasinglulu /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 618*91f16700Schasinglulu #define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ 619*91f16700Schasinglulu #define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ 620*91f16700Schasinglulu #define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ 621*91f16700Schasinglulu /* SPM_SRC_REQ (0x10006000+0x0B8) */ 622*91f16700Schasinglulu #define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 623*91f16700Schasinglulu #define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 624*91f16700Schasinglulu #define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 625*91f16700Schasinglulu #define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 626*91f16700Schasinglulu #define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ 627*91f16700Schasinglulu #define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ 628*91f16700Schasinglulu #define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ 629*91f16700Schasinglulu #define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ 630*91f16700Schasinglulu /* SPM_SRC_MASK (0x10006000+0x0BC) */ 631*91f16700Schasinglulu #define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ 632*91f16700Schasinglulu #define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ 633*91f16700Schasinglulu #define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ 634*91f16700Schasinglulu #define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ 635*91f16700Schasinglulu #define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ 636*91f16700Schasinglulu #define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ 637*91f16700Schasinglulu #define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ 638*91f16700Schasinglulu #define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ 639*91f16700Schasinglulu #define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ 640*91f16700Schasinglulu #define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ 641*91f16700Schasinglulu #define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ 642*91f16700Schasinglulu #define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ 643*91f16700Schasinglulu #define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ 644*91f16700Schasinglulu #define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ 645*91f16700Schasinglulu #define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ 646*91f16700Schasinglulu #define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ 647*91f16700Schasinglulu #define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ 648*91f16700Schasinglulu #define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 649*91f16700Schasinglulu #define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ 650*91f16700Schasinglulu #define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ 651*91f16700Schasinglulu #define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 652*91f16700Schasinglulu #define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 653*91f16700Schasinglulu #define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ 654*91f16700Schasinglulu #define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ 655*91f16700Schasinglulu #define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 656*91f16700Schasinglulu #define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 657*91f16700Schasinglulu #define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ 658*91f16700Schasinglulu #define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ 659*91f16700Schasinglulu /* SPM_SRC2_MASK (0x10006000+0x0C0) */ 660*91f16700Schasinglulu #define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ 661*91f16700Schasinglulu #define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ 662*91f16700Schasinglulu #define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ 663*91f16700Schasinglulu #define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ 664*91f16700Schasinglulu #define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ 665*91f16700Schasinglulu #define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ 666*91f16700Schasinglulu #define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ 667*91f16700Schasinglulu #define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ 668*91f16700Schasinglulu #define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ 669*91f16700Schasinglulu #define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ 670*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ 671*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 672*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ 673*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ 674*91f16700Schasinglulu /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ 675*91f16700Schasinglulu #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 676*91f16700Schasinglulu /* SCP_CLK_CON (0x10006000+0x0D0) */ 677*91f16700Schasinglulu #define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 678*91f16700Schasinglulu #define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ 679*91f16700Schasinglulu #define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ 680*91f16700Schasinglulu #define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ 681*91f16700Schasinglulu /* PCM_DEBUG_CON (0x10006000+0x0D4) */ 682*91f16700Schasinglulu #define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ 683*91f16700Schasinglulu /* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ 684*91f16700Schasinglulu #define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ 685*91f16700Schasinglulu #define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ 686*91f16700Schasinglulu #define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ 687*91f16700Schasinglulu /* AHB_BUS_CON (0x10006000+0x0DC) */ 688*91f16700Schasinglulu #define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ 689*91f16700Schasinglulu #define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ 690*91f16700Schasinglulu /* SPM_SRC3_MASK (0x10006000+0x0E0) */ 691*91f16700Schasinglulu #define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ 692*91f16700Schasinglulu #define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ 693*91f16700Schasinglulu #define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ 694*91f16700Schasinglulu #define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ 695*91f16700Schasinglulu #define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ 696*91f16700Schasinglulu #define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ 697*91f16700Schasinglulu #define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ 698*91f16700Schasinglulu #define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ 699*91f16700Schasinglulu #define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ 700*91f16700Schasinglulu #define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ 701*91f16700Schasinglulu /* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ 702*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ 703*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ 704*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ 705*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ 706*91f16700Schasinglulu /* SSPM_CLK_CON (0x10006000+0x0E8) */ 707*91f16700Schasinglulu #define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ 708*91f16700Schasinglulu /* PCM_REG0_DATA (0x10006000+0x100) */ 709*91f16700Schasinglulu #define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ 710*91f16700Schasinglulu /* PCM_REG1_DATA (0x10006000+0x104) */ 711*91f16700Schasinglulu #define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ 712*91f16700Schasinglulu /* PCM_REG2_DATA (0x10006000+0x108) */ 713*91f16700Schasinglulu #define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ 714*91f16700Schasinglulu /* PCM_REG3_DATA (0x10006000+0x10C) */ 715*91f16700Schasinglulu #define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ 716*91f16700Schasinglulu /* PCM_REG4_DATA (0x10006000+0x110) */ 717*91f16700Schasinglulu #define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ 718*91f16700Schasinglulu /* PCM_REG5_DATA (0x10006000+0x114) */ 719*91f16700Schasinglulu #define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ 720*91f16700Schasinglulu /* PCM_REG6_DATA (0x10006000+0x118) */ 721*91f16700Schasinglulu #define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ 722*91f16700Schasinglulu /* PCM_REG7_DATA (0x10006000+0x11C) */ 723*91f16700Schasinglulu #define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ 724*91f16700Schasinglulu /* PCM_REG8_DATA (0x10006000+0x120) */ 725*91f16700Schasinglulu #define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ 726*91f16700Schasinglulu /* PCM_REG9_DATA (0x10006000+0x124) */ 727*91f16700Schasinglulu #define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ 728*91f16700Schasinglulu /* PCM_REG10_DATA (0x10006000+0x128) */ 729*91f16700Schasinglulu #define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ 730*91f16700Schasinglulu /* PCM_REG11_DATA (0x10006000+0x12C) */ 731*91f16700Schasinglulu #define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ 732*91f16700Schasinglulu /* PCM_REG12_DATA (0x10006000+0x130) */ 733*91f16700Schasinglulu #define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ 734*91f16700Schasinglulu /* PCM_REG13_DATA (0x10006000+0x134) */ 735*91f16700Schasinglulu #define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ 736*91f16700Schasinglulu /* PCM_REG14_DATA (0x10006000+0x138) */ 737*91f16700Schasinglulu #define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ 738*91f16700Schasinglulu /* PCM_REG15_DATA (0x10006000+0x13C) */ 739*91f16700Schasinglulu #define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ 740*91f16700Schasinglulu /* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ 741*91f16700Schasinglulu #define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ 742*91f16700Schasinglulu /* PCM_REG12_EXT_DATA (0x10006000+0x144) */ 743*91f16700Schasinglulu #define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ 744*91f16700Schasinglulu /* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ 745*91f16700Schasinglulu #define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ 746*91f16700Schasinglulu /* PCM_EVENT_REG_STA (0x10006000+0x14C) */ 747*91f16700Schasinglulu #define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ 748*91f16700Schasinglulu /* PCM_TIMER_OUT (0x10006000+0x150) */ 749*91f16700Schasinglulu #define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ 750*91f16700Schasinglulu /* PCM_WDT_OUT (0x10006000+0x154) */ 751*91f16700Schasinglulu #define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ 752*91f16700Schasinglulu /* SPM_IRQ_STA (0x10006000+0x158) */ 753*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ 754*91f16700Schasinglulu #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 755*91f16700Schasinglulu #define PCM_IRQ_LSB (1U << 3) /* 1b */ 756*91f16700Schasinglulu /* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ 757*91f16700Schasinglulu /* SPM_WAKEUP_STA (0x10006000+0x15C) */ 758*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ 759*91f16700Schasinglulu /* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ 760*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ 761*91f16700Schasinglulu /* SPM_WAKEUP_MISC (0x10006000+0x164) */ 762*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ 763*91f16700Schasinglulu #define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ 764*91f16700Schasinglulu #define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ 765*91f16700Schasinglulu /* BUS_PROTECT_RDY (0x10006000+0x168) */ 766*91f16700Schasinglulu #define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ 767*91f16700Schasinglulu /* BUS_PROTECT2_RDY (0x10006000+0x16C) */ 768*91f16700Schasinglulu #define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ 769*91f16700Schasinglulu /* SUBSYS_IDLE_STA (0x10006000+0x170) */ 770*91f16700Schasinglulu #define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ 771*91f16700Schasinglulu /* CPU_IDLE_STA (0x10006000+0x174) */ 772*91f16700Schasinglulu #define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ 773*91f16700Schasinglulu #define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ 774*91f16700Schasinglulu #define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ 775*91f16700Schasinglulu #define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ 776*91f16700Schasinglulu #define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ 777*91f16700Schasinglulu #define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ 778*91f16700Schasinglulu #define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ 779*91f16700Schasinglulu #define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ 780*91f16700Schasinglulu #define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ 781*91f16700Schasinglulu #define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ 782*91f16700Schasinglulu #define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ 783*91f16700Schasinglulu #define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ 784*91f16700Schasinglulu #define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ 785*91f16700Schasinglulu #define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ 786*91f16700Schasinglulu #define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ 787*91f16700Schasinglulu #define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ 788*91f16700Schasinglulu #define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ 789*91f16700Schasinglulu #define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ 790*91f16700Schasinglulu #define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ 791*91f16700Schasinglulu #define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ 792*91f16700Schasinglulu /* PCM_FSM_STA (0x10006000+0x178) */ 793*91f16700Schasinglulu #define EXEC_INST_OP_LSB (1U << 0) /* 4b */ 794*91f16700Schasinglulu #define PC_STATE_LSB (1U << 4) /* 3b */ 795*91f16700Schasinglulu #define IM_STATE_LSB (1U << 7) /* 3b */ 796*91f16700Schasinglulu #define MASTER_STATE_LSB (1U << 10) /* 5b */ 797*91f16700Schasinglulu #define EVENT_FSM_LSB (1U << 15) /* 3b */ 798*91f16700Schasinglulu #define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ 799*91f16700Schasinglulu #define PCM_KICK_LSB (1U << 21) /* 1b */ 800*91f16700Schasinglulu #define IM_KICK_LSB (1U << 22) /* 1b */ 801*91f16700Schasinglulu #define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ 802*91f16700Schasinglulu #define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ 803*91f16700Schasinglulu /* SRC_REQ_STA (0x10006000+0x17C) */ 804*91f16700Schasinglulu #define SRC_REQ_STA_LSB (1U << 0) /* 32b */ 805*91f16700Schasinglulu /* PWR_STATUS (0x10006000+0x180) */ 806*91f16700Schasinglulu #define PWR_STATUS_LSB (1U << 0) /* 32b */ 807*91f16700Schasinglulu /* PWR_STATUS_2ND (0x10006000+0x184) */ 808*91f16700Schasinglulu #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 809*91f16700Schasinglulu /* CPU_PWR_STATUS (0x10006000+0x188) */ 810*91f16700Schasinglulu #define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ 811*91f16700Schasinglulu /* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ 812*91f16700Schasinglulu #define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 813*91f16700Schasinglulu /* MISC_STA (0x10006000+0x190) */ 814*91f16700Schasinglulu #define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ 815*91f16700Schasinglulu /* SPM_SRC_RDY_STA (0x10006000+0x194) */ 816*91f16700Schasinglulu #define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ 817*91f16700Schasinglulu #define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ 818*91f16700Schasinglulu /* DRAMC_DBG_LATCH (0x10006000+0x19C) */ 819*91f16700Schasinglulu #define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ 820*91f16700Schasinglulu /* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ 821*91f16700Schasinglulu #define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ 822*91f16700Schasinglulu /* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ 823*91f16700Schasinglulu #define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ 824*91f16700Schasinglulu /* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ 825*91f16700Schasinglulu #define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ 826*91f16700Schasinglulu /* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ 827*91f16700Schasinglulu #define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ 828*91f16700Schasinglulu /* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ 829*91f16700Schasinglulu #define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ 830*91f16700Schasinglulu /* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ 831*91f16700Schasinglulu #define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ 832*91f16700Schasinglulu /* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ 833*91f16700Schasinglulu #define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ 834*91f16700Schasinglulu /* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ 835*91f16700Schasinglulu #define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ 836*91f16700Schasinglulu /* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ 837*91f16700Schasinglulu #define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ 838*91f16700Schasinglulu /* SPM_DVFS_STA (0x10006000+0x1C8) */ 839*91f16700Schasinglulu #define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ 840*91f16700Schasinglulu /* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ 841*91f16700Schasinglulu #define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ 842*91f16700Schasinglulu #define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ 843*91f16700Schasinglulu /* SRC_DDREN_STA (0x10006000+0x1E0) */ 844*91f16700Schasinglulu #define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ 845*91f16700Schasinglulu /* MCU_PWR_CON (0x10006000+0x200) */ 846*91f16700Schasinglulu #define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ 847*91f16700Schasinglulu #define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ 848*91f16700Schasinglulu #define MCU_PWR_ON_LSB (1U << 2) /* 1b */ 849*91f16700Schasinglulu #define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 850*91f16700Schasinglulu #define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 851*91f16700Schasinglulu #define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ 852*91f16700Schasinglulu #define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 853*91f16700Schasinglulu #define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 854*91f16700Schasinglulu #define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ 855*91f16700Schasinglulu #define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 856*91f16700Schasinglulu #define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 857*91f16700Schasinglulu #define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 858*91f16700Schasinglulu /* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ 859*91f16700Schasinglulu #define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 860*91f16700Schasinglulu #define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ 861*91f16700Schasinglulu #define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ 862*91f16700Schasinglulu #define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 863*91f16700Schasinglulu #define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 864*91f16700Schasinglulu #define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 865*91f16700Schasinglulu #define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 866*91f16700Schasinglulu #define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 867*91f16700Schasinglulu #define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ 868*91f16700Schasinglulu #define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 869*91f16700Schasinglulu #define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 870*91f16700Schasinglulu #define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 871*91f16700Schasinglulu /* MP0_CPU0_PWR_CON (0x10006000+0x208) */ 872*91f16700Schasinglulu #define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ 873*91f16700Schasinglulu #define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ 874*91f16700Schasinglulu #define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ 875*91f16700Schasinglulu #define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 876*91f16700Schasinglulu #define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 877*91f16700Schasinglulu #define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 878*91f16700Schasinglulu #define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 879*91f16700Schasinglulu #define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 880*91f16700Schasinglulu #define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ 881*91f16700Schasinglulu #define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 882*91f16700Schasinglulu #define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 883*91f16700Schasinglulu #define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 884*91f16700Schasinglulu /* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ 885*91f16700Schasinglulu #define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ 886*91f16700Schasinglulu #define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ 887*91f16700Schasinglulu #define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ 888*91f16700Schasinglulu #define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 889*91f16700Schasinglulu #define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 890*91f16700Schasinglulu #define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 891*91f16700Schasinglulu #define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 892*91f16700Schasinglulu #define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 893*91f16700Schasinglulu #define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ 894*91f16700Schasinglulu #define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 895*91f16700Schasinglulu #define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 896*91f16700Schasinglulu #define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 897*91f16700Schasinglulu /* MP0_CPU2_PWR_CON (0x10006000+0x210) */ 898*91f16700Schasinglulu #define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ 899*91f16700Schasinglulu #define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ 900*91f16700Schasinglulu #define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ 901*91f16700Schasinglulu #define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 902*91f16700Schasinglulu #define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 903*91f16700Schasinglulu #define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 904*91f16700Schasinglulu #define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 905*91f16700Schasinglulu #define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 906*91f16700Schasinglulu #define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ 907*91f16700Schasinglulu #define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 908*91f16700Schasinglulu #define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 909*91f16700Schasinglulu #define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 910*91f16700Schasinglulu /* MP0_CPU3_PWR_CON (0x10006000+0x214) */ 911*91f16700Schasinglulu #define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ 912*91f16700Schasinglulu #define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ 913*91f16700Schasinglulu #define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ 914*91f16700Schasinglulu #define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 915*91f16700Schasinglulu #define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 916*91f16700Schasinglulu #define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ 917*91f16700Schasinglulu #define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 918*91f16700Schasinglulu #define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 919*91f16700Schasinglulu #define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ 920*91f16700Schasinglulu #define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 921*91f16700Schasinglulu #define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 922*91f16700Schasinglulu #define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 923*91f16700Schasinglulu /* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ 924*91f16700Schasinglulu #define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 925*91f16700Schasinglulu #define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ 926*91f16700Schasinglulu #define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ 927*91f16700Schasinglulu #define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 928*91f16700Schasinglulu #define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 929*91f16700Schasinglulu #define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 930*91f16700Schasinglulu #define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 931*91f16700Schasinglulu #define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 932*91f16700Schasinglulu #define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ 933*91f16700Schasinglulu #define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 934*91f16700Schasinglulu #define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 935*91f16700Schasinglulu #define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 936*91f16700Schasinglulu /* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ 937*91f16700Schasinglulu #define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ 938*91f16700Schasinglulu #define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ 939*91f16700Schasinglulu #define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ 940*91f16700Schasinglulu #define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 941*91f16700Schasinglulu #define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 942*91f16700Schasinglulu #define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 943*91f16700Schasinglulu #define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 944*91f16700Schasinglulu #define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 945*91f16700Schasinglulu #define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ 946*91f16700Schasinglulu #define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 947*91f16700Schasinglulu #define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 948*91f16700Schasinglulu #define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 949*91f16700Schasinglulu /* MP1_CPU1_PWR_CON (0x10006000+0x220) */ 950*91f16700Schasinglulu #define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ 951*91f16700Schasinglulu #define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ 952*91f16700Schasinglulu #define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ 953*91f16700Schasinglulu #define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 954*91f16700Schasinglulu #define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 955*91f16700Schasinglulu #define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 956*91f16700Schasinglulu #define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 957*91f16700Schasinglulu #define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 958*91f16700Schasinglulu #define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ 959*91f16700Schasinglulu #define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 960*91f16700Schasinglulu #define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 961*91f16700Schasinglulu #define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 962*91f16700Schasinglulu /* MP1_CPU2_PWR_CON (0x10006000+0x224) */ 963*91f16700Schasinglulu #define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ 964*91f16700Schasinglulu #define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ 965*91f16700Schasinglulu #define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ 966*91f16700Schasinglulu #define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 967*91f16700Schasinglulu #define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 968*91f16700Schasinglulu #define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 969*91f16700Schasinglulu #define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 970*91f16700Schasinglulu #define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 971*91f16700Schasinglulu #define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ 972*91f16700Schasinglulu #define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 973*91f16700Schasinglulu #define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 974*91f16700Schasinglulu #define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 975*91f16700Schasinglulu /* MP1_CPU3_PWR_CON (0x10006000+0x228) */ 976*91f16700Schasinglulu #define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ 977*91f16700Schasinglulu #define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ 978*91f16700Schasinglulu #define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ 979*91f16700Schasinglulu #define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 980*91f16700Schasinglulu #define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 981*91f16700Schasinglulu #define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ 982*91f16700Schasinglulu #define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 983*91f16700Schasinglulu #define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 984*91f16700Schasinglulu #define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ 985*91f16700Schasinglulu #define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 986*91f16700Schasinglulu #define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 987*91f16700Schasinglulu #define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 988*91f16700Schasinglulu /* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ 989*91f16700Schasinglulu #define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ 990*91f16700Schasinglulu #define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ 991*91f16700Schasinglulu /* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ 992*91f16700Schasinglulu #define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ 993*91f16700Schasinglulu #define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ 994*91f16700Schasinglulu /* MP0_CPU0_L1_PDN (0x10006000+0x248) */ 995*91f16700Schasinglulu #define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ 996*91f16700Schasinglulu #define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 997*91f16700Schasinglulu /* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ 998*91f16700Schasinglulu #define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ 999*91f16700Schasinglulu #define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1000*91f16700Schasinglulu /* MP0_CPU2_L1_PDN (0x10006000+0x250) */ 1001*91f16700Schasinglulu #define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ 1002*91f16700Schasinglulu #define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1003*91f16700Schasinglulu /* MP0_CPU3_L1_PDN (0x10006000+0x254) */ 1004*91f16700Schasinglulu #define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ 1005*91f16700Schasinglulu #define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1006*91f16700Schasinglulu /* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ 1007*91f16700Schasinglulu #define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ 1008*91f16700Schasinglulu #define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ 1009*91f16700Schasinglulu /* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ 1010*91f16700Schasinglulu #define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ 1011*91f16700Schasinglulu #define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ 1012*91f16700Schasinglulu /* MP1_CPU0_L1_PDN (0x10006000+0x260) */ 1013*91f16700Schasinglulu #define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ 1014*91f16700Schasinglulu #define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1015*91f16700Schasinglulu /* MP1_CPU1_L1_PDN (0x10006000+0x264) */ 1016*91f16700Schasinglulu #define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ 1017*91f16700Schasinglulu #define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1018*91f16700Schasinglulu /* MP1_CPU2_L1_PDN (0x10006000+0x268) */ 1019*91f16700Schasinglulu #define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ 1020*91f16700Schasinglulu #define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1021*91f16700Schasinglulu /* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ 1022*91f16700Schasinglulu #define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ 1023*91f16700Schasinglulu #define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1024*91f16700Schasinglulu /* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ 1025*91f16700Schasinglulu #define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1026*91f16700Schasinglulu #define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1027*91f16700Schasinglulu #define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ 1028*91f16700Schasinglulu /* DUMMY1_PWR_CON (0x10006000+0x2B0) */ 1029*91f16700Schasinglulu #define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1030*91f16700Schasinglulu #define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ 1031*91f16700Schasinglulu #define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ 1032*91f16700Schasinglulu #define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1033*91f16700Schasinglulu #define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1034*91f16700Schasinglulu /* BYPASS_SPMC (0x10006000+0x2B4) */ 1035*91f16700Schasinglulu #define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ 1036*91f16700Schasinglulu /* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ 1037*91f16700Schasinglulu #define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ 1038*91f16700Schasinglulu #define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ 1039*91f16700Schasinglulu /* ARMPLL_CLK_CON (0x10006000+0x2BC) */ 1040*91f16700Schasinglulu #define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ 1041*91f16700Schasinglulu #define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ 1042*91f16700Schasinglulu #define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ 1043*91f16700Schasinglulu #define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ 1044*91f16700Schasinglulu #define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ 1045*91f16700Schasinglulu /* SPMC_IN_RET (0x10006000+0x2C0) */ 1046*91f16700Schasinglulu #define SPMC_STATUS_LSB (1U << 0) /* 8b */ 1047*91f16700Schasinglulu /* VDE_PWR_CON (0x10006000+0x300) */ 1048*91f16700Schasinglulu #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1049*91f16700Schasinglulu #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 1050*91f16700Schasinglulu #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 1051*91f16700Schasinglulu #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1052*91f16700Schasinglulu #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1053*91f16700Schasinglulu #define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ 1054*91f16700Schasinglulu #define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1055*91f16700Schasinglulu /* VEN_PWR_CON (0x10006000+0x304) */ 1056*91f16700Schasinglulu #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1057*91f16700Schasinglulu #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 1058*91f16700Schasinglulu #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 1059*91f16700Schasinglulu #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1060*91f16700Schasinglulu #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1061*91f16700Schasinglulu #define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ 1062*91f16700Schasinglulu #define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1063*91f16700Schasinglulu /* ISP_PWR_CON (0x10006000+0x308) */ 1064*91f16700Schasinglulu #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1065*91f16700Schasinglulu #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 1066*91f16700Schasinglulu #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 1067*91f16700Schasinglulu #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1068*91f16700Schasinglulu #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1069*91f16700Schasinglulu #define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ 1070*91f16700Schasinglulu #define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1071*91f16700Schasinglulu /* DIS_PWR_CON (0x10006000+0x30C) */ 1072*91f16700Schasinglulu #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 1073*91f16700Schasinglulu #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 1074*91f16700Schasinglulu #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 1075*91f16700Schasinglulu #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1076*91f16700Schasinglulu #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1077*91f16700Schasinglulu #define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ 1078*91f16700Schasinglulu #define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1079*91f16700Schasinglulu /* MFG_CORE1_PWR_CON (0x10006000+0x310) */ 1080*91f16700Schasinglulu #define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1081*91f16700Schasinglulu #define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1082*91f16700Schasinglulu #define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1083*91f16700Schasinglulu #define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1084*91f16700Schasinglulu #define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1085*91f16700Schasinglulu #define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ 1086*91f16700Schasinglulu #define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1087*91f16700Schasinglulu /* AUDIO_PWR_CON (0x10006000+0x314) */ 1088*91f16700Schasinglulu #define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ 1089*91f16700Schasinglulu #define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ 1090*91f16700Schasinglulu #define AUD_PWR_ON_LSB (1U << 2) /* 1b */ 1091*91f16700Schasinglulu #define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1092*91f16700Schasinglulu #define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1093*91f16700Schasinglulu #define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ 1094*91f16700Schasinglulu #define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1095*91f16700Schasinglulu /* IFR_PWR_CON (0x10006000+0x318) */ 1096*91f16700Schasinglulu #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 1097*91f16700Schasinglulu #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 1098*91f16700Schasinglulu #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 1099*91f16700Schasinglulu #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1100*91f16700Schasinglulu #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1101*91f16700Schasinglulu #define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ 1102*91f16700Schasinglulu #define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1103*91f16700Schasinglulu /* DPY_PWR_CON (0x10006000+0x31C) */ 1104*91f16700Schasinglulu #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 1105*91f16700Schasinglulu #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 1106*91f16700Schasinglulu #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 1107*91f16700Schasinglulu #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1108*91f16700Schasinglulu #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1109*91f16700Schasinglulu #define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ 1110*91f16700Schasinglulu #define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1111*91f16700Schasinglulu /* MD1_PWR_CON (0x10006000+0x320) */ 1112*91f16700Schasinglulu #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1113*91f16700Schasinglulu #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 1114*91f16700Schasinglulu #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 1115*91f16700Schasinglulu #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1116*91f16700Schasinglulu #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1117*91f16700Schasinglulu #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1118*91f16700Schasinglulu /* VPU_TOP_PWR_CON (0x10006000+0x324) */ 1119*91f16700Schasinglulu #define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1120*91f16700Schasinglulu #define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ 1121*91f16700Schasinglulu #define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ 1122*91f16700Schasinglulu #define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1123*91f16700Schasinglulu #define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1124*91f16700Schasinglulu #define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1125*91f16700Schasinglulu #define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1126*91f16700Schasinglulu #define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ 1127*91f16700Schasinglulu #define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1128*91f16700Schasinglulu #define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1129*91f16700Schasinglulu #define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1130*91f16700Schasinglulu /* CONN_PWR_CON (0x10006000+0x32C) */ 1131*91f16700Schasinglulu #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1132*91f16700Schasinglulu #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 1133*91f16700Schasinglulu #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 1134*91f16700Schasinglulu #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1135*91f16700Schasinglulu #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1136*91f16700Schasinglulu #define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ 1137*91f16700Schasinglulu #define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1138*91f16700Schasinglulu /* VPU_CORE2_PWR_CON (0x10006000+0x330) */ 1139*91f16700Schasinglulu #define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1140*91f16700Schasinglulu #define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ 1141*91f16700Schasinglulu #define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ 1142*91f16700Schasinglulu #define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1143*91f16700Schasinglulu #define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1144*91f16700Schasinglulu #define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1145*91f16700Schasinglulu #define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1146*91f16700Schasinglulu #define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ 1147*91f16700Schasinglulu #define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1148*91f16700Schasinglulu #define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1149*91f16700Schasinglulu #define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1150*91f16700Schasinglulu /* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ 1151*91f16700Schasinglulu #define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1152*91f16700Schasinglulu #define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ 1153*91f16700Schasinglulu #define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ 1154*91f16700Schasinglulu #define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1155*91f16700Schasinglulu #define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1156*91f16700Schasinglulu #define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ 1157*91f16700Schasinglulu #define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1158*91f16700Schasinglulu /* MFG_PWR_CON (0x10006000+0x338) */ 1159*91f16700Schasinglulu #define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ 1160*91f16700Schasinglulu #define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ 1161*91f16700Schasinglulu #define MFG_PWR_ON_LSB (1U << 2) /* 1b */ 1162*91f16700Schasinglulu #define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1163*91f16700Schasinglulu #define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1164*91f16700Schasinglulu #define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ 1165*91f16700Schasinglulu #define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1166*91f16700Schasinglulu /* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ 1167*91f16700Schasinglulu #define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1168*91f16700Schasinglulu #define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ 1169*91f16700Schasinglulu #define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ 1170*91f16700Schasinglulu #define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ 1171*91f16700Schasinglulu #define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ 1172*91f16700Schasinglulu #define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1173*91f16700Schasinglulu #define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1174*91f16700Schasinglulu #define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ 1175*91f16700Schasinglulu #define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1176*91f16700Schasinglulu #define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1177*91f16700Schasinglulu #define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1178*91f16700Schasinglulu /* VPU_CORE1_PWR_CON (0x10006000+0x340) */ 1179*91f16700Schasinglulu #define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1180*91f16700Schasinglulu #define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1181*91f16700Schasinglulu #define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1182*91f16700Schasinglulu #define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ 1183*91f16700Schasinglulu #define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ 1184*91f16700Schasinglulu #define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1185*91f16700Schasinglulu #define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1186*91f16700Schasinglulu #define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ 1187*91f16700Schasinglulu #define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1188*91f16700Schasinglulu #define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1189*91f16700Schasinglulu #define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1190*91f16700Schasinglulu /* CAM_PWR_CON (0x10006000+0x344) */ 1191*91f16700Schasinglulu #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1192*91f16700Schasinglulu #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 1193*91f16700Schasinglulu #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 1194*91f16700Schasinglulu #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1195*91f16700Schasinglulu #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1196*91f16700Schasinglulu #define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ 1197*91f16700Schasinglulu #define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1198*91f16700Schasinglulu /* MFG_2D_PWR_CON (0x10006000+0x348) */ 1199*91f16700Schasinglulu #define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ 1200*91f16700Schasinglulu #define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ 1201*91f16700Schasinglulu #define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ 1202*91f16700Schasinglulu #define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1203*91f16700Schasinglulu #define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1204*91f16700Schasinglulu #define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ 1205*91f16700Schasinglulu #define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1206*91f16700Schasinglulu /* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ 1207*91f16700Schasinglulu #define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1208*91f16700Schasinglulu #define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ 1209*91f16700Schasinglulu #define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ 1210*91f16700Schasinglulu #define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1211*91f16700Schasinglulu #define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1212*91f16700Schasinglulu #define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ 1213*91f16700Schasinglulu #define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1214*91f16700Schasinglulu /* SYSRAM_CON (0x10006000+0x350) */ 1215*91f16700Schasinglulu #define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1216*91f16700Schasinglulu #define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1217*91f16700Schasinglulu #define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1218*91f16700Schasinglulu #define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ 1219*91f16700Schasinglulu /* SYSROM_CON (0x10006000+0x354) */ 1220*91f16700Schasinglulu #define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ 1221*91f16700Schasinglulu /* SSPM_SRAM_CON (0x10006000+0x358) */ 1222*91f16700Schasinglulu #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1223*91f16700Schasinglulu #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1224*91f16700Schasinglulu #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1225*91f16700Schasinglulu #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1226*91f16700Schasinglulu /* SCP_SRAM_CON (0x10006000+0x35C) */ 1227*91f16700Schasinglulu #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1228*91f16700Schasinglulu #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1229*91f16700Schasinglulu #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1230*91f16700Schasinglulu #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1231*91f16700Schasinglulu /* UFS_SRAM_CON (0x10006000+0x36C) */ 1232*91f16700Schasinglulu #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1233*91f16700Schasinglulu #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1234*91f16700Schasinglulu #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1235*91f16700Schasinglulu #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ 1236*91f16700Schasinglulu /* DUMMY_SRAM_CON (0x10006000+0x380) */ 1237*91f16700Schasinglulu #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1238*91f16700Schasinglulu #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1239*91f16700Schasinglulu #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1240*91f16700Schasinglulu #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ 1241*91f16700Schasinglulu /* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ 1242*91f16700Schasinglulu #define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ 1243*91f16700Schasinglulu #define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ 1244*91f16700Schasinglulu /* MD_SRAM_ISO_CON (0x10006000+0x394) */ 1245*91f16700Schasinglulu #define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ 1246*91f16700Schasinglulu /* MD_EXTRA_PWR_CON (0x10006000+0x398) */ 1247*91f16700Schasinglulu #define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ 1248*91f16700Schasinglulu #define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ 1249*91f16700Schasinglulu /* EXT_BUCK_CON (0x10006000+0x3A0) */ 1250*91f16700Schasinglulu #define RG_VA09_ON_LSB (1U << 0) /* 1b */ 1251*91f16700Schasinglulu /* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ 1252*91f16700Schasinglulu #define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ 1253*91f16700Schasinglulu /* SPM_DVFS_CON (0x10006000+0x400) */ 1254*91f16700Schasinglulu #define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ 1255*91f16700Schasinglulu #define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ 1256*91f16700Schasinglulu /* SPM_MDBSI_CON (0x10006000+0x404) */ 1257*91f16700Schasinglulu #define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ 1258*91f16700Schasinglulu /* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ 1259*91f16700Schasinglulu #define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ 1260*91f16700Schasinglulu /* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ 1261*91f16700Schasinglulu #define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ 1262*91f16700Schasinglulu /* SPM_BSI_GEN (0x10006000+0x410) */ 1263*91f16700Schasinglulu #define SPM_BSI_START_LSB (1U << 0) /* 1b */ 1264*91f16700Schasinglulu /* SPM_BSI_EN_SR (0x10006000+0x414) */ 1265*91f16700Schasinglulu #define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ 1266*91f16700Schasinglulu /* SPM_BSI_CLK_SR (0x10006000+0x418) */ 1267*91f16700Schasinglulu #define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ 1268*91f16700Schasinglulu /* SPM_BSI_D0_SR (0x10006000+0x41C) */ 1269*91f16700Schasinglulu #define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ 1270*91f16700Schasinglulu /* SPM_BSI_D1_SR (0x10006000+0x420) */ 1271*91f16700Schasinglulu #define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ 1272*91f16700Schasinglulu /* SPM_BSI_D2_SR (0x10006000+0x424) */ 1273*91f16700Schasinglulu #define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ 1274*91f16700Schasinglulu /* SPM_AP_SEMA (0x10006000+0x428) */ 1275*91f16700Schasinglulu #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 1276*91f16700Schasinglulu /* SPM_SPM_SEMA (0x10006000+0x42C) */ 1277*91f16700Schasinglulu #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 1278*91f16700Schasinglulu /* AP_MDSRC_REQ (0x10006000+0x430) */ 1279*91f16700Schasinglulu #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1280*91f16700Schasinglulu #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1281*91f16700Schasinglulu #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1282*91f16700Schasinglulu #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1283*91f16700Schasinglulu #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1284*91f16700Schasinglulu #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1285*91f16700Schasinglulu /* SPM2MD_DVFS_CON (0x10006000+0x438) */ 1286*91f16700Schasinglulu #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1287*91f16700Schasinglulu /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ 1288*91f16700Schasinglulu #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1289*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ 1290*91f16700Schasinglulu #define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ 1291*91f16700Schasinglulu #define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ 1292*91f16700Schasinglulu #define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ 1293*91f16700Schasinglulu #define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ 1294*91f16700Schasinglulu #define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ 1295*91f16700Schasinglulu #define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ 1296*91f16700Schasinglulu #define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ 1297*91f16700Schasinglulu /* DPY_LP_CON (0x10006000+0x444) */ 1298*91f16700Schasinglulu #define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ 1299*91f16700Schasinglulu /* CPU_DVFS_REQ (0x10006000+0x448) */ 1300*91f16700Schasinglulu #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ 1301*91f16700Schasinglulu /* SPM_PLL_CON (0x10006000+0x44C) */ 1302*91f16700Schasinglulu #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1303*91f16700Schasinglulu #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1304*91f16700Schasinglulu #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1305*91f16700Schasinglulu #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1306*91f16700Schasinglulu #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1307*91f16700Schasinglulu #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1308*91f16700Schasinglulu #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1309*91f16700Schasinglulu #define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ 1310*91f16700Schasinglulu /* SPM_EMI_BW_MODE (0x10006000+0x450) */ 1311*91f16700Schasinglulu #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1312*91f16700Schasinglulu #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1313*91f16700Schasinglulu #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1314*91f16700Schasinglulu #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1315*91f16700Schasinglulu /* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ 1316*91f16700Schasinglulu #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1317*91f16700Schasinglulu /* ULPOSC_CON (0x10006000+0x458) */ 1318*91f16700Schasinglulu #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1319*91f16700Schasinglulu #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1320*91f16700Schasinglulu #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1321*91f16700Schasinglulu #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1322*91f16700Schasinglulu /* SPM2MM_CON (0x10006000+0x45C) */ 1323*91f16700Schasinglulu #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1324*91f16700Schasinglulu #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1325*91f16700Schasinglulu #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1326*91f16700Schasinglulu #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1327*91f16700Schasinglulu #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1328*91f16700Schasinglulu #define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ 1329*91f16700Schasinglulu #define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ 1330*91f16700Schasinglulu #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1331*91f16700Schasinglulu #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1332*91f16700Schasinglulu #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1333*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ 1334*91f16700Schasinglulu #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ 1335*91f16700Schasinglulu #define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ 1336*91f16700Schasinglulu #define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ 1337*91f16700Schasinglulu #define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ 1338*91f16700Schasinglulu #define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ 1339*91f16700Schasinglulu #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ 1340*91f16700Schasinglulu #define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ 1341*91f16700Schasinglulu #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ 1342*91f16700Schasinglulu #define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ 1343*91f16700Schasinglulu #define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ 1344*91f16700Schasinglulu #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ 1345*91f16700Schasinglulu #define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ 1346*91f16700Schasinglulu #define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ 1347*91f16700Schasinglulu #define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ 1348*91f16700Schasinglulu #define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ 1349*91f16700Schasinglulu #define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ 1350*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ 1351*91f16700Schasinglulu #define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ 1352*91f16700Schasinglulu #define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ 1353*91f16700Schasinglulu #define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ 1354*91f16700Schasinglulu #define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ 1355*91f16700Schasinglulu #define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ 1356*91f16700Schasinglulu #define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ 1357*91f16700Schasinglulu #define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ 1358*91f16700Schasinglulu #define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ 1359*91f16700Schasinglulu #define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ 1360*91f16700Schasinglulu #define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ 1361*91f16700Schasinglulu #define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ 1362*91f16700Schasinglulu #define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ 1363*91f16700Schasinglulu #define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ 1364*91f16700Schasinglulu #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ 1365*91f16700Schasinglulu #define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ 1366*91f16700Schasinglulu /* SPM_S1_MODE_CH (0x10006000+0x468) */ 1367*91f16700Schasinglulu #define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ 1368*91f16700Schasinglulu #define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ 1369*91f16700Schasinglulu /* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ 1370*91f16700Schasinglulu #define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ 1371*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ 1372*91f16700Schasinglulu #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ 1373*91f16700Schasinglulu #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ 1374*91f16700Schasinglulu #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ 1375*91f16700Schasinglulu #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ 1376*91f16700Schasinglulu #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ 1377*91f16700Schasinglulu #define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ 1378*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ 1379*91f16700Schasinglulu #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ 1380*91f16700Schasinglulu #define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ 1381*91f16700Schasinglulu #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ 1382*91f16700Schasinglulu #define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ 1383*91f16700Schasinglulu #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ 1384*91f16700Schasinglulu /* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ 1385*91f16700Schasinglulu #define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ 1386*91f16700Schasinglulu #define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ 1387*91f16700Schasinglulu #define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ 1388*91f16700Schasinglulu #define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ 1389*91f16700Schasinglulu #define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ 1390*91f16700Schasinglulu #define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ 1391*91f16700Schasinglulu #define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ 1392*91f16700Schasinglulu #define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ 1393*91f16700Schasinglulu #define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ 1394*91f16700Schasinglulu #define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ 1395*91f16700Schasinglulu #define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ 1396*91f16700Schasinglulu #define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ 1397*91f16700Schasinglulu /* DRAMC_DMYRD_CON (0x10006000+0x478) */ 1398*91f16700Schasinglulu #define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ 1399*91f16700Schasinglulu #define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ 1400*91f16700Schasinglulu #define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ 1401*91f16700Schasinglulu #define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ 1402*91f16700Schasinglulu #define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ 1403*91f16700Schasinglulu #define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ 1404*91f16700Schasinglulu /* SPM_DRS_CON (0x10006000+0x47C) */ 1405*91f16700Schasinglulu #define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ 1406*91f16700Schasinglulu #define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ 1407*91f16700Schasinglulu #define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ 1408*91f16700Schasinglulu #define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ 1409*91f16700Schasinglulu /* SPM_SEMA_M0 (0x10006000+0x480) */ 1410*91f16700Schasinglulu #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 1411*91f16700Schasinglulu /* SPM_SEMA_M1 (0x10006000+0x484) */ 1412*91f16700Schasinglulu #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 1413*91f16700Schasinglulu /* SPM_SEMA_M2 (0x10006000+0x488) */ 1414*91f16700Schasinglulu #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 1415*91f16700Schasinglulu /* SPM_SEMA_M3 (0x10006000+0x48C) */ 1416*91f16700Schasinglulu #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 1417*91f16700Schasinglulu /* SPM_SEMA_M4 (0x10006000+0x490) */ 1418*91f16700Schasinglulu #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 1419*91f16700Schasinglulu /* SPM_SEMA_M5 (0x10006000+0x494) */ 1420*91f16700Schasinglulu #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 1421*91f16700Schasinglulu /* SPM_SEMA_M6 (0x10006000+0x498) */ 1422*91f16700Schasinglulu #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 1423*91f16700Schasinglulu /* SPM_SEMA_M7 (0x10006000+0x49C) */ 1424*91f16700Schasinglulu #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 1425*91f16700Schasinglulu /* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ 1426*91f16700Schasinglulu #define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ 1427*91f16700Schasinglulu /* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ 1428*91f16700Schasinglulu #define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ 1429*91f16700Schasinglulu /* SRAM_DREQ_ACK (0x10006000+0x4AC) */ 1430*91f16700Schasinglulu #define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ 1431*91f16700Schasinglulu /* SRAM_DREQ_CON (0x10006000+0x4B0) */ 1432*91f16700Schasinglulu #define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ 1433*91f16700Schasinglulu /* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ 1434*91f16700Schasinglulu #define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ 1435*91f16700Schasinglulu /* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ 1436*91f16700Schasinglulu #define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ 1437*91f16700Schasinglulu /* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ 1438*91f16700Schasinglulu #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1439*91f16700Schasinglulu /* SPM_SSPM_IRQ (0x10006000+0x4C0) */ 1440*91f16700Schasinglulu #define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ 1441*91f16700Schasinglulu #define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ 1442*91f16700Schasinglulu /* SPM2PMCU_INT (0x10006000+0x4C4) */ 1443*91f16700Schasinglulu #define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ 1444*91f16700Schasinglulu /* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ 1445*91f16700Schasinglulu #define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ 1446*91f16700Schasinglulu /* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ 1447*91f16700Schasinglulu #define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ 1448*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ 1449*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 1450*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ 1451*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 1452*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ 1453*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 1454*91f16700Schasinglulu /* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ 1455*91f16700Schasinglulu #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 1456*91f16700Schasinglulu /* PMCU2SPM_INT (0x10006000+0x4E0) */ 1457*91f16700Schasinglulu #define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ 1458*91f16700Schasinglulu /* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ 1459*91f16700Schasinglulu #define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1460*91f16700Schasinglulu /* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ 1461*91f16700Schasinglulu #define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1462*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ 1463*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1464*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ 1465*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1466*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ 1467*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1468*91f16700Schasinglulu /* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ 1469*91f16700Schasinglulu #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1470*91f16700Schasinglulu /* PMCU2SPM_CFG (0x10006000+0x4FC) */ 1471*91f16700Schasinglulu #define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1472*91f16700Schasinglulu #define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ 1473*91f16700Schasinglulu /* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ 1474*91f16700Schasinglulu #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1475*91f16700Schasinglulu #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ 1476*91f16700Schasinglulu /* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ 1477*91f16700Schasinglulu #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1478*91f16700Schasinglulu #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ 1479*91f16700Schasinglulu /* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ 1480*91f16700Schasinglulu #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1481*91f16700Schasinglulu #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ 1482*91f16700Schasinglulu /* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ 1483*91f16700Schasinglulu #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1484*91f16700Schasinglulu #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ 1485*91f16700Schasinglulu /* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ 1486*91f16700Schasinglulu #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1487*91f16700Schasinglulu #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ 1488*91f16700Schasinglulu /* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ 1489*91f16700Schasinglulu #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1490*91f16700Schasinglulu #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ 1491*91f16700Schasinglulu /* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ 1492*91f16700Schasinglulu #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1493*91f16700Schasinglulu #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ 1494*91f16700Schasinglulu /* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ 1495*91f16700Schasinglulu #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1496*91f16700Schasinglulu #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ 1497*91f16700Schasinglulu /* MP0_CPU0_WFI_EN (0x10006000+0x530) */ 1498*91f16700Schasinglulu #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1499*91f16700Schasinglulu /* MP0_CPU1_WFI_EN (0x10006000+0x534) */ 1500*91f16700Schasinglulu #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1501*91f16700Schasinglulu /* MP0_CPU2_WFI_EN (0x10006000+0x538) */ 1502*91f16700Schasinglulu #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1503*91f16700Schasinglulu /* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ 1504*91f16700Schasinglulu #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1505*91f16700Schasinglulu /* MP1_CPU0_WFI_EN (0x10006000+0x540) */ 1506*91f16700Schasinglulu #define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1507*91f16700Schasinglulu /* MP1_CPU1_WFI_EN (0x10006000+0x544) */ 1508*91f16700Schasinglulu #define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1509*91f16700Schasinglulu /* MP1_CPU2_WFI_EN (0x10006000+0x548) */ 1510*91f16700Schasinglulu #define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1511*91f16700Schasinglulu /* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ 1512*91f16700Schasinglulu #define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1513*91f16700Schasinglulu /* MP0_L2CFLUSH (0x10006000+0x554) */ 1514*91f16700Schasinglulu #define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ 1515*91f16700Schasinglulu #define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ 1516*91f16700Schasinglulu /* MP1_L2CFLUSH (0x10006000+0x558) */ 1517*91f16700Schasinglulu #define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ 1518*91f16700Schasinglulu #define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ 1519*91f16700Schasinglulu /* CPU_PTPOD2_CON (0x10006000+0x560) */ 1520*91f16700Schasinglulu #define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ 1521*91f16700Schasinglulu #define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ 1522*91f16700Schasinglulu #define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ 1523*91f16700Schasinglulu #define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ 1524*91f16700Schasinglulu #define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ 1525*91f16700Schasinglulu #define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ 1526*91f16700Schasinglulu /* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ 1527*91f16700Schasinglulu #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 1528*91f16700Schasinglulu /* ROOT_CORE_ADDR (0x10006000+0x574) */ 1529*91f16700Schasinglulu #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 1530*91f16700Schasinglulu /* CPU_SPARE_CON (0x10006000+0x580) */ 1531*91f16700Schasinglulu #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 1532*91f16700Schasinglulu /* CPU_SPARE_CON_SET (0x10006000+0x584) */ 1533*91f16700Schasinglulu #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1534*91f16700Schasinglulu /* CPU_SPARE_CON_CLR (0x10006000+0x588) */ 1535*91f16700Schasinglulu #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1536*91f16700Schasinglulu /* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ 1537*91f16700Schasinglulu #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 1538*91f16700Schasinglulu /* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ 1539*91f16700Schasinglulu #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 1540*91f16700Schasinglulu /* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ 1541*91f16700Schasinglulu #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 1542*91f16700Schasinglulu /* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ 1543*91f16700Schasinglulu #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 1544*91f16700Schasinglulu /* SW2SPM_INT (0x10006000+0x5E0) */ 1545*91f16700Schasinglulu #define SW2SPM_INT_LSB (1U << 0) /* 4b */ 1546*91f16700Schasinglulu /* SW2SPM_INT_SET (0x10006000+0x5E4) */ 1547*91f16700Schasinglulu #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1548*91f16700Schasinglulu /* SW2SPM_INT_CLR (0x10006000+0x5E8) */ 1549*91f16700Schasinglulu #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1550*91f16700Schasinglulu /* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ 1551*91f16700Schasinglulu #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1552*91f16700Schasinglulu /* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ 1553*91f16700Schasinglulu #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1554*91f16700Schasinglulu /* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ 1555*91f16700Schasinglulu #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1556*91f16700Schasinglulu /* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ 1557*91f16700Schasinglulu #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1558*91f16700Schasinglulu /* SW2SPM_CFG (0x10006000+0x5FC) */ 1559*91f16700Schasinglulu #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1560*91f16700Schasinglulu #define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ 1561*91f16700Schasinglulu /* SPM_SW_FLAG (0x10006000+0x600) */ 1562*91f16700Schasinglulu #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 1563*91f16700Schasinglulu /* SPM_SW_DEBUG (0x10006000+0x604) */ 1564*91f16700Schasinglulu #define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ 1565*91f16700Schasinglulu /* SPM_SW_RSV_0 (0x10006000+0x608) */ 1566*91f16700Schasinglulu #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 1567*91f16700Schasinglulu /* SPM_SW_RSV_1 (0x10006000+0x60C) */ 1568*91f16700Schasinglulu #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 1569*91f16700Schasinglulu /* SPM_SW_RSV_2 (0x10006000+0x610) */ 1570*91f16700Schasinglulu #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 1571*91f16700Schasinglulu /* SPM_SW_RSV_3 (0x10006000+0x614) */ 1572*91f16700Schasinglulu #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 1573*91f16700Schasinglulu /* SPM_SW_RSV_4 (0x10006000+0x618) */ 1574*91f16700Schasinglulu #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 1575*91f16700Schasinglulu /* SPM_SW_RSV_5 (0x10006000+0x61C) */ 1576*91f16700Schasinglulu #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 1577*91f16700Schasinglulu /* SPM_RSV_CON (0x10006000+0x620) */ 1578*91f16700Schasinglulu #define SPM_RSV_CON_LSB (1U << 0) /* 16b */ 1579*91f16700Schasinglulu /* SPM_RSV_STA (0x10006000+0x624) */ 1580*91f16700Schasinglulu #define SPM_RSV_STA_LSB (1U << 0) /* 16b */ 1581*91f16700Schasinglulu /* SPM_RSV_CON1 (0x10006000+0x628) */ 1582*91f16700Schasinglulu #define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ 1583*91f16700Schasinglulu /* SPM_RSV_STA1 (0x10006000+0x62C) */ 1584*91f16700Schasinglulu #define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ 1585*91f16700Schasinglulu /* SPM_PASR_DPD_0 (0x10006000+0x630) */ 1586*91f16700Schasinglulu #define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ 1587*91f16700Schasinglulu /* SPM_PASR_DPD_1 (0x10006000+0x634) */ 1588*91f16700Schasinglulu #define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ 1589*91f16700Schasinglulu /* SPM_PASR_DPD_2 (0x10006000+0x638) */ 1590*91f16700Schasinglulu #define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ 1591*91f16700Schasinglulu /* SPM_PASR_DPD_3 (0x10006000+0x63C) */ 1592*91f16700Schasinglulu #define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ 1593*91f16700Schasinglulu /* SPM_SPARE_CON (0x10006000+0x640) */ 1594*91f16700Schasinglulu #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 1595*91f16700Schasinglulu /* SPM_SPARE_CON_SET (0x10006000+0x644) */ 1596*91f16700Schasinglulu #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1597*91f16700Schasinglulu /* SPM_SPARE_CON_CLR (0x10006000+0x648) */ 1598*91f16700Schasinglulu #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1599*91f16700Schasinglulu /* SPM_SW_RSV_6 (0x10006000+0x64C) */ 1600*91f16700Schasinglulu #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 1601*91f16700Schasinglulu /* SPM_SW_RSV_7 (0x10006000+0x650) */ 1602*91f16700Schasinglulu #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 1603*91f16700Schasinglulu /* SPM_SW_RSV_8 (0x10006000+0x654) */ 1604*91f16700Schasinglulu #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 1605*91f16700Schasinglulu /* SPM_SW_RSV_9 (0x10006000+0x658) */ 1606*91f16700Schasinglulu #define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ 1607*91f16700Schasinglulu /* SPM_SW_RSV_10 (0x10006000+0x65C) */ 1608*91f16700Schasinglulu #define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ 1609*91f16700Schasinglulu /* SPM_SW_RSV_18 (0x10006000+0x67C) */ 1610*91f16700Schasinglulu #define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ 1611*91f16700Schasinglulu /* SPM_SW_RSV_19 (0x10006000+0x680) */ 1612*91f16700Schasinglulu #define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ 1613*91f16700Schasinglulu /* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ 1614*91f16700Schasinglulu #define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ 1615*91f16700Schasinglulu #define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ 1616*91f16700Schasinglulu /* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ 1617*91f16700Schasinglulu #define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ 1618*91f16700Schasinglulu #define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ 1619*91f16700Schasinglulu /* DVFSRC_EVENT_SEL (0x10006000+0x698) */ 1620*91f16700Schasinglulu #define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ 1621*91f16700Schasinglulu /* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ 1622*91f16700Schasinglulu #define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ 1623*91f16700Schasinglulu /* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ 1624*91f16700Schasinglulu #define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ 1625*91f16700Schasinglulu /* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ 1626*91f16700Schasinglulu #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ 1627*91f16700Schasinglulu /* DVFS_ABORT_STA (0x10006000+0x6A8) */ 1628*91f16700Schasinglulu #define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ 1629*91f16700Schasinglulu #define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ 1630*91f16700Schasinglulu /* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ 1631*91f16700Schasinglulu #define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ 1632*91f16700Schasinglulu /* SPM_DFS_LEVEL (0x10006000+0x6B0) */ 1633*91f16700Schasinglulu #define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ 1634*91f16700Schasinglulu /* SPM_DVS_LEVEL (0x10006000+0x6B4) */ 1635*91f16700Schasinglulu #define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ 1636*91f16700Schasinglulu #define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ 1637*91f16700Schasinglulu #define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ 1638*91f16700Schasinglulu /* SPM_DVFS_MISC (0x10006000+0x6B8) */ 1639*91f16700Schasinglulu #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 1640*91f16700Schasinglulu #define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ 1641*91f16700Schasinglulu #define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ 1642*91f16700Schasinglulu #define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ 1643*91f16700Schasinglulu #define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ 1644*91f16700Schasinglulu /* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ 1645*91f16700Schasinglulu #define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ 1646*91f16700Schasinglulu #define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ 1647*91f16700Schasinglulu #define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ 1648*91f16700Schasinglulu #define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ 1649*91f16700Schasinglulu #define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ 1650*91f16700Schasinglulu #define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ 1651*91f16700Schasinglulu #define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ 1652*91f16700Schasinglulu #define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ 1653*91f16700Schasinglulu #define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ 1654*91f16700Schasinglulu #define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 1655*91f16700Schasinglulu #define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 1656*91f16700Schasinglulu #define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ 1657*91f16700Schasinglulu /* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ 1658*91f16700Schasinglulu #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ 1659*91f16700Schasinglulu /* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ 1660*91f16700Schasinglulu #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 1661*91f16700Schasinglulu #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 1662*91f16700Schasinglulu /* SPARE_ACK_STA (0x10006000+0x6F0) */ 1663*91f16700Schasinglulu #define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ 1664*91f16700Schasinglulu /* SPARE_ACK_MASK (0x10006000+0x6F4) */ 1665*91f16700Schasinglulu #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 1666*91f16700Schasinglulu /* SPM_DVFS_CON1 (0x10006000+0x700) */ 1667*91f16700Schasinglulu #define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ 1668*91f16700Schasinglulu /* SPM_DVFS_CON1_STA (0x10006000+0x704) */ 1669*91f16700Schasinglulu #define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ 1670*91f16700Schasinglulu /* SPM_DVFS_CMD0 (0x10006000+0x710) */ 1671*91f16700Schasinglulu #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 1672*91f16700Schasinglulu /* SPM_DVFS_CMD1 (0x10006000+0x714) */ 1673*91f16700Schasinglulu #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 1674*91f16700Schasinglulu /* SPM_DVFS_CMD2 (0x10006000+0x718) */ 1675*91f16700Schasinglulu #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 1676*91f16700Schasinglulu /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ 1677*91f16700Schasinglulu #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 1678*91f16700Schasinglulu /* SPM_DVFS_CMD4 (0x10006000+0x720) */ 1679*91f16700Schasinglulu #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 1680*91f16700Schasinglulu /* SPM_DVFS_CMD5 (0x10006000+0x724) */ 1681*91f16700Schasinglulu #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 1682*91f16700Schasinglulu /* SPM_DVFS_CMD6 (0x10006000+0x728) */ 1683*91f16700Schasinglulu #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 1684*91f16700Schasinglulu /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ 1685*91f16700Schasinglulu #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 1686*91f16700Schasinglulu /* SPM_DVFS_CMD8 (0x10006000+0x730) */ 1687*91f16700Schasinglulu #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 1688*91f16700Schasinglulu /* SPM_DVFS_CMD9 (0x10006000+0x734) */ 1689*91f16700Schasinglulu #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 1690*91f16700Schasinglulu /* SPM_DVFS_CMD10 (0x10006000+0x738) */ 1691*91f16700Schasinglulu #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 1692*91f16700Schasinglulu /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ 1693*91f16700Schasinglulu #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 1694*91f16700Schasinglulu /* SPM_DVFS_CMD12 (0x10006000+0x740) */ 1695*91f16700Schasinglulu #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 1696*91f16700Schasinglulu /* SPM_DVFS_CMD13 (0x10006000+0x744) */ 1697*91f16700Schasinglulu #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 1698*91f16700Schasinglulu /* SPM_DVFS_CMD14 (0x10006000+0x748) */ 1699*91f16700Schasinglulu #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 1700*91f16700Schasinglulu /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ 1701*91f16700Schasinglulu #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 1702*91f16700Schasinglulu /* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ 1703*91f16700Schasinglulu #define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ 1704*91f16700Schasinglulu /* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ 1705*91f16700Schasinglulu #define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ 1706*91f16700Schasinglulu /* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ 1707*91f16700Schasinglulu #define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ 1708*91f16700Schasinglulu /* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ 1709*91f16700Schasinglulu #define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ 1710*91f16700Schasinglulu /* SPARE_ACK_IN_FIX (0x10006000+0x790) */ 1711*91f16700Schasinglulu #define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ 1712*91f16700Schasinglulu /* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ 1713*91f16700Schasinglulu #define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ 1714*91f16700Schasinglulu /* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ 1715*91f16700Schasinglulu #define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ 1716*91f16700Schasinglulu /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ 1717*91f16700Schasinglulu #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 1718*91f16700Schasinglulu /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ 1719*91f16700Schasinglulu #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 1720*91f16700Schasinglulu /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ 1721*91f16700Schasinglulu #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 1722*91f16700Schasinglulu /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ 1723*91f16700Schasinglulu #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 1724*91f16700Schasinglulu /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ 1725*91f16700Schasinglulu #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 1726*91f16700Schasinglulu /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ 1727*91f16700Schasinglulu #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 1728*91f16700Schasinglulu /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ 1729*91f16700Schasinglulu #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 1730*91f16700Schasinglulu /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ 1731*91f16700Schasinglulu #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 1732*91f16700Schasinglulu /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ 1733*91f16700Schasinglulu #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 1734*91f16700Schasinglulu /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ 1735*91f16700Schasinglulu #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 1736*91f16700Schasinglulu /* WDT_LATCH_SPARE0 (0x10006000+0x828) */ 1737*91f16700Schasinglulu #define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ 1738*91f16700Schasinglulu /* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ 1739*91f16700Schasinglulu #define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ 1740*91f16700Schasinglulu /* WDT_LATCH_SPARE2 (0x10006000+0x830) */ 1741*91f16700Schasinglulu #define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ 1742*91f16700Schasinglulu /* WDT_LATCH_SPARE3 (0x10006000+0x834) */ 1743*91f16700Schasinglulu #define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ 1744*91f16700Schasinglulu /* PCM_WDT_LATCH_10 (0x10006000+0x838) */ 1745*91f16700Schasinglulu #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 1746*91f16700Schasinglulu /* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ 1747*91f16700Schasinglulu #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 1748*91f16700Schasinglulu /* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ 1749*91f16700Schasinglulu #define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ 1750*91f16700Schasinglulu /* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ 1751*91f16700Schasinglulu #define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ 1752*91f16700Schasinglulu /* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ 1753*91f16700Schasinglulu #define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ 1754*91f16700Schasinglulu /* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ 1755*91f16700Schasinglulu #define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ 1756*91f16700Schasinglulu /* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ 1757*91f16700Schasinglulu #define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ 1758*91f16700Schasinglulu /* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ 1759*91f16700Schasinglulu #define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ 1760*91f16700Schasinglulu /* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ 1761*91f16700Schasinglulu #define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ 1762*91f16700Schasinglulu /* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ 1763*91f16700Schasinglulu #define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ 1764*91f16700Schasinglulu /* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ 1765*91f16700Schasinglulu #define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ 1766*91f16700Schasinglulu /* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ 1767*91f16700Schasinglulu #define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ 1768*91f16700Schasinglulu /* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ 1769*91f16700Schasinglulu #define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ 1770*91f16700Schasinglulu /* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ 1771*91f16700Schasinglulu #define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ 1772*91f16700Schasinglulu /* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ 1773*91f16700Schasinglulu #define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ 1774*91f16700Schasinglulu /* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ 1775*91f16700Schasinglulu #define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ 1776*91f16700Schasinglulu /* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ 1777*91f16700Schasinglulu #define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ 1778*91f16700Schasinglulu /* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ 1779*91f16700Schasinglulu #define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ 1780*91f16700Schasinglulu /* DCHA_LATCH_RSV0 (0x10006000+0x880) */ 1781*91f16700Schasinglulu #define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ 1782*91f16700Schasinglulu /* DCHB_LATCH_RSV0 (0x10006000+0x884) */ 1783*91f16700Schasinglulu #define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ 1784*91f16700Schasinglulu /* PCM_WDT_LATCH_12 (0x10006000+0x888) */ 1785*91f16700Schasinglulu #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 1786*91f16700Schasinglulu /* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ 1787*91f16700Schasinglulu #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 1788*91f16700Schasinglulu /* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ 1789*91f16700Schasinglulu #define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ 1790*91f16700Schasinglulu #define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ 1791*91f16700Schasinglulu #define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ 1792*91f16700Schasinglulu /* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ 1793*91f16700Schasinglulu #define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ 1794*91f16700Schasinglulu #define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ 1795*91f16700Schasinglulu /* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ 1796*91f16700Schasinglulu #define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ 1797*91f16700Schasinglulu #define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ 1798*91f16700Schasinglulu /* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ 1799*91f16700Schasinglulu #define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ 1800*91f16700Schasinglulu #define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ 1801*91f16700Schasinglulu /* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ 1802*91f16700Schasinglulu #define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ 1803*91f16700Schasinglulu #define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ 1804*91f16700Schasinglulu /* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ 1805*91f16700Schasinglulu #define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ 1806*91f16700Schasinglulu #define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ 1807*91f16700Schasinglulu /* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ 1808*91f16700Schasinglulu #define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ 1809*91f16700Schasinglulu #define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ 1810*91f16700Schasinglulu /* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ 1811*91f16700Schasinglulu #define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ 1812*91f16700Schasinglulu #define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ 1813*91f16700Schasinglulu /* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ 1814*91f16700Schasinglulu #define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ 1815*91f16700Schasinglulu #define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ 1816*91f16700Schasinglulu /* SPM_ACK_CHK_CON (0x10006000+0x900) */ 1817*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ 1818*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ 1819*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ 1820*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ 1821*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ 1822*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ 1823*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ 1824*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ 1825*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ 1826*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ 1827*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ 1828*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ 1829*91f16700Schasinglulu /* SPM_ACK_CHK_PC (0x10006000+0x904) */ 1830*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ 1831*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ 1832*91f16700Schasinglulu /* SPM_ACK_CHK_SEL (0x10006000+0x908) */ 1833*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ 1834*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ 1835*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ 1836*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ 1837*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ 1838*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ 1839*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ 1840*91f16700Schasinglulu /* SPM_ACK_CHK_STA (0x10006000+0x910) */ 1841*91f16700Schasinglulu #define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ 1842*91f16700Schasinglulu /* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ 1843*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ 1844*91f16700Schasinglulu /* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ 1845*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ 1846*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ 1847*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ 1848*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ 1849*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ 1850*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ 1851*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ 1852*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ 1853*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ 1854*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ 1855*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ 1856*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ 1857*91f16700Schasinglulu /* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ 1858*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ 1859*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ 1860*91f16700Schasinglulu /* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ 1861*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ 1862*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ 1863*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ 1864*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ 1865*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ 1866*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ 1867*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ 1868*91f16700Schasinglulu /* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ 1869*91f16700Schasinglulu #define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ 1870*91f16700Schasinglulu /* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ 1871*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ 1872*91f16700Schasinglulu /* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ 1873*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ 1874*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ 1875*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ 1876*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ 1877*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ 1878*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ 1879*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ 1880*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ 1881*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ 1882*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ 1883*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ 1884*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ 1885*91f16700Schasinglulu /* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ 1886*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ 1887*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ 1888*91f16700Schasinglulu /* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ 1889*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ 1890*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ 1891*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ 1892*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ 1893*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ 1894*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ 1895*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ 1896*91f16700Schasinglulu /* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ 1897*91f16700Schasinglulu #define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ 1898*91f16700Schasinglulu /* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ 1899*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ 1900*91f16700Schasinglulu /* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ 1901*91f16700Schasinglulu #define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ 1902*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ 1903*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ 1904*91f16700Schasinglulu #define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ 1905*91f16700Schasinglulu #define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ 1906*91f16700Schasinglulu #define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ 1907*91f16700Schasinglulu #define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ 1908*91f16700Schasinglulu #define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ 1909*91f16700Schasinglulu #define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ 1910*91f16700Schasinglulu #define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ 1911*91f16700Schasinglulu #define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ 1912*91f16700Schasinglulu #define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ 1913*91f16700Schasinglulu /* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ 1914*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ 1915*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ 1916*91f16700Schasinglulu /* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ 1917*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ 1918*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ 1919*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ 1920*91f16700Schasinglulu #define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ 1921*91f16700Schasinglulu /* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ 1922*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ 1923*91f16700Schasinglulu #define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ 1924*91f16700Schasinglulu /* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ 1925*91f16700Schasinglulu #define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ 1926*91f16700Schasinglulu /* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ 1927*91f16700Schasinglulu #define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ 1928*91f16700Schasinglulu 1929*91f16700Schasinglulu /* --- SPM Flag Define --- */ 1930*91f16700Schasinglulu #define SPM_FLAG_DIS_CPU_PDN (1U << 0) 1931*91f16700Schasinglulu #define SPM_FLAG_DIS_INFRA_PDN (1U << 1) 1932*91f16700Schasinglulu #define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) 1933*91f16700Schasinglulu #define SPM_FLAG_DIS_VCORE_DVS (1U << 3) 1934*91f16700Schasinglulu #define SPM_FLAG_DIS_VCORE_DFS (1U << 4) 1935*91f16700Schasinglulu #define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) 1936*91f16700Schasinglulu #define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) 1937*91f16700Schasinglulu #define SPM_FLAG_DIS_ATF_ABORT (1U << 7) 1938*91f16700Schasinglulu #define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) 1939*91f16700Schasinglulu #define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) 1940*91f16700Schasinglulu #define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) 1941*91f16700Schasinglulu #define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) 1942*91f16700Schasinglulu #define SPM_FLAG_SODI_CG_MODE (1U << 12) 1943*91f16700Schasinglulu #define SPM_FLAG_SODI_NO_EVENT (1U << 13) 1944*91f16700Schasinglulu #define SPM_FLAG_ENABLE_SODI3 (1U << 14) 1945*91f16700Schasinglulu #define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) 1946*91f16700Schasinglulu #define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) 1947*91f16700Schasinglulu #define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) 1948*91f16700Schasinglulu #define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) 1949*91f16700Schasinglulu #define SPM_FLAG_SUSPEND_OPTION (1U << 19) 1950*91f16700Schasinglulu #define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) 1951*91f16700Schasinglulu #define SPM_FLAG_SODI_OPTION (1U << 21) 1952*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) 1953*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) 1954*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) 1955*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) 1956*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) 1957*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) 1958*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) 1959*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) 1960*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) 1961*91f16700Schasinglulu #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) 1962*91f16700Schasinglulu 1963*91f16700Schasinglulu /* --- SPM Flag1 Define --- */ 1964*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT0 (1U << 0) 1965*91f16700Schasinglulu #define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) 1966*91f16700Schasinglulu #define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) 1967*91f16700Schasinglulu #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) 1968*91f16700Schasinglulu #define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) 1969*91f16700Schasinglulu #define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) 1970*91f16700Schasinglulu #define SPM_FLAG1_DISABLE_MCDSR (1U << 6) 1971*91f16700Schasinglulu #define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) 1972*91f16700Schasinglulu #define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) 1973*91f16700Schasinglulu #define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) 1974*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT10 (1U << 10) 1975*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT11 (1U << 11) 1976*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT12 (1U << 12) 1977*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT13 (1U << 13) 1978*91f16700Schasinglulu #define SPM_FLAG1_RESERVED_BIT14 (1U << 14) 1979*91f16700Schasinglulu #define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) 1980*91f16700Schasinglulu #define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) 1981*91f16700Schasinglulu #define SPM_FLAG1_DIS_IMP_DIS (1U << 17) 1982*91f16700Schasinglulu #define SPM_FLAG1_DIS_IMP_COPY (1U << 18) 1983*91f16700Schasinglulu #define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) 1984*91f16700Schasinglulu #define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) 1985*91f16700Schasinglulu #define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) 1986*91f16700Schasinglulu #define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) 1987*91f16700Schasinglulu #define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) 1988*91f16700Schasinglulu #define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) 1989*91f16700Schasinglulu #define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) 1990*91f16700Schasinglulu #define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) 1991*91f16700Schasinglulu #define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) 1992*91f16700Schasinglulu #define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) 1993*91f16700Schasinglulu #define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) 1994*91f16700Schasinglulu #define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) 1995*91f16700Schasinglulu #define SPM_FLAG1_DIS_SW_MR4 (1U << 31) 1996*91f16700Schasinglulu 1997*91f16700Schasinglulu /* --- SPM DEBUG Define --- */ 1998*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) 1999*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) 2000*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) 2001*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) 2002*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) 2003*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) 2004*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) 2005*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) 2006*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) 2007*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) 2008*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) 2009*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) 2010*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) 2011*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_DPD (1U << 13) 2012*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) 2013*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) 2014*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) 2015*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) 2016*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) 2017*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) 2018*91f16700Schasinglulu #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) 2019*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT21 (1U << 21) 2020*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT22 (1U << 22) 2021*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT23 (1U << 23) 2022*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT24 (1U << 24) 2023*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT25 (1U << 25) 2024*91f16700Schasinglulu #define SPM_DBG_RESERVED_BIT26 (1U << 26) 2025*91f16700Schasinglulu #define SPM_DBG_SODI1_FLAG (1U << 27) 2026*91f16700Schasinglulu #define SPM_DBG_SODI3_FLAG (1U << 28) 2027*91f16700Schasinglulu #define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) 2028*91f16700Schasinglulu #define SPM_DBG_DEEPIDLE_FLAG (1U << 30) 2029*91f16700Schasinglulu #define SPM_DBG_SUSPEND_FLAG (1U << 31) 2030*91f16700Schasinglulu 2031*91f16700Schasinglulu /* --- SPM DEBUG1 Define --- */ 2032*91f16700Schasinglulu #define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) 2033*91f16700Schasinglulu #define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) 2034*91f16700Schasinglulu #define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) 2035*91f16700Schasinglulu #define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) 2036*91f16700Schasinglulu #define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) 2037*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT5 (1U << 5) 2038*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT6 (1U << 6) 2039*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT7 (1U << 7) 2040*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT8 (1U << 8) 2041*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT9 (1U << 9) 2042*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT10 (1U << 10) 2043*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT11 (1U << 11) 2044*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT12 (1U << 12) 2045*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT13 (1U << 13) 2046*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT14 (1U << 14) 2047*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT15 (1U << 15) 2048*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT16 (1U << 16) 2049*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT17 (1U << 17) 2050*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT18 (1U << 18) 2051*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT19 (1U << 19) 2052*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT20 (1U << 20) 2053*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT21 (1U << 21) 2054*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT22 (1U << 22) 2055*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT23 (1U << 23) 2056*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT24 (1U << 24) 2057*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT25 (1U << 25) 2058*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT26 (1U << 26) 2059*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT27 (1U << 27) 2060*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT28 (1U << 28) 2061*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT29 (1U << 29) 2062*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT30 (1U << 30) 2063*91f16700Schasinglulu #define SPM_DBG1_RESERVED_BIT31 (1U << 31) 2064*91f16700Schasinglulu 2065*91f16700Schasinglulu /* --- R0 Define --- */ 2066*91f16700Schasinglulu #define R0_SC_26M_CK_OFF (1U << 0) 2067*91f16700Schasinglulu #define R0_BIT1 (1U << 1) 2068*91f16700Schasinglulu #define R0_SC_MEM_CK_OFF (1U << 2) 2069*91f16700Schasinglulu #define R0_SC_AXI_CK_OFF (1U << 3) 2070*91f16700Schasinglulu #define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) 2071*91f16700Schasinglulu #define R0_SC_MD26M_CK_OFF (1U << 5) 2072*91f16700Schasinglulu #define R0_SC_DPY_MODE_SW_PCM (1U << 6) 2073*91f16700Schasinglulu #define R0_SC_DMSUS_OFF_PCM (1U << 7) 2074*91f16700Schasinglulu #define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) 2075*91f16700Schasinglulu #define R0_BIT9 (1U << 9) 2076*91f16700Schasinglulu #define R0_SC_MPLLOUT_OFF (1U << 10) 2077*91f16700Schasinglulu #define R0_SC_TX_TRACKING_DIS (1U << 11) 2078*91f16700Schasinglulu #define R0_SC_DPY_DLL_EN_PCM (1U << 12) 2079*91f16700Schasinglulu #define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) 2080*91f16700Schasinglulu #define R0_SC_DPY_VREF_EN_PCM (1U << 14) 2081*91f16700Schasinglulu #define R0_SC_PHYPLL_EN_PCM (1U << 15) 2082*91f16700Schasinglulu #define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) 2083*91f16700Schasinglulu #define R0_SC_DPY_BCLK_ENABLE (1U << 17) 2084*91f16700Schasinglulu #define R0_SC_MPLL_OFF (1U << 18) 2085*91f16700Schasinglulu #define R0_SC_SHU_RESTORE (1U << 19) 2086*91f16700Schasinglulu #define R0_SC_CKSQ0_OFF (1U << 20) 2087*91f16700Schasinglulu #define R0_SC_CKSQ1_OFF (1U << 21) 2088*91f16700Schasinglulu #define R0_SC_DR_SHU_EN_PCM (1U << 22) 2089*91f16700Schasinglulu #define R0_SC_DPHY_PRECAL_UP (1U << 23) 2090*91f16700Schasinglulu #define R0_SC_MPLL_S_OFF (1U << 24) 2091*91f16700Schasinglulu #define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) 2092*91f16700Schasinglulu #define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) 2093*91f16700Schasinglulu #define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) 2094*91f16700Schasinglulu #define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) 2095*91f16700Schasinglulu #define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) 2096*91f16700Schasinglulu #define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) 2097*91f16700Schasinglulu #define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) 2098*91f16700Schasinglulu 2099*91f16700Schasinglulu /* --- R7 Define --- */ 2100*91f16700Schasinglulu #define R7_PWRAP_SLEEP_REQ (1U << 0) 2101*91f16700Schasinglulu #define R7_EMI_CLK_OFF_REQ (1U << 1) 2102*91f16700Schasinglulu #define R7_TOP_MAS_PAU_REQ (1U << 2) 2103*91f16700Schasinglulu #define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) 2104*91f16700Schasinglulu #define R7_PCM_CK_SEL0 (1U << 4) 2105*91f16700Schasinglulu #define R7_PCM_CK_SEL1 (1U << 5) 2106*91f16700Schasinglulu #define R7_SPM2RC_DVS_DONE (1U << 6) 2107*91f16700Schasinglulu #define R7_FREQH_PAUSE_MPLL (1U << 7) 2108*91f16700Schasinglulu #define R7_SC_26M_CK_SEL (1U << 8) 2109*91f16700Schasinglulu #define R7_PCM_TIMER_SET (1U << 9) 2110*91f16700Schasinglulu #define R7_PCM_TIMER_CLR (1U << 10) 2111*91f16700Schasinglulu #define R7_SRCVOLTEN (1U << 11) 2112*91f16700Schasinglulu #define R7_CSYSPWRUPACK (1U << 12) 2113*91f16700Schasinglulu #define R7_IM_SLEEP_ENABLE (1U << 13) 2114*91f16700Schasinglulu #define R7_SRCCLKENO_0 (1U << 14) 2115*91f16700Schasinglulu #define R7_SYSRST (1U << 15) 2116*91f16700Schasinglulu #define R7_MD_APSRC_ACK (1U << 16) 2117*91f16700Schasinglulu #define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) 2118*91f16700Schasinglulu #define R7_SC_AXI_DCM_DIS (1U << 18) 2119*91f16700Schasinglulu #define R7_FREQH_PAUSE_MAIN (1U << 19) 2120*91f16700Schasinglulu #define R7_FREQH_PAUSE_MEM (1U << 20) 2121*91f16700Schasinglulu #define R7_SRCCLKENO_1 (1U << 21) 2122*91f16700Schasinglulu #define R7_WDT_KICK_P (1U << 22) 2123*91f16700Schasinglulu #define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) 2124*91f16700Schasinglulu #define R7_WAKEUP_EXT_W_SEL (1U << 24) 2125*91f16700Schasinglulu #define R7_WAKEUP_EXT_R_SEL (1U << 25) 2126*91f16700Schasinglulu #define R7_PMIC_IRQ_REQ_EN (1U << 26) 2127*91f16700Schasinglulu #define R7_FORCE_26M_WAKE (1U << 27) 2128*91f16700Schasinglulu #define R7_FORCE_APSRC_WAKE (1U << 28) 2129*91f16700Schasinglulu #define R7_FORCE_INFRA_WAKE (1U << 29) 2130*91f16700Schasinglulu #define R7_FORCE_VRF18_WAKE (1U << 30) 2131*91f16700Schasinglulu #define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) 2132*91f16700Schasinglulu 2133*91f16700Schasinglulu /* --- R12 Define --- */ 2134*91f16700Schasinglulu #define R12_PCM_TIMER (1U << 0) 2135*91f16700Schasinglulu #define R12_SSPM_WDT_EVENT_B (1U << 1) 2136*91f16700Schasinglulu #define R12_KP_IRQ_B (1U << 2) 2137*91f16700Schasinglulu #define R12_APWDT_EVENT_B (1U << 3) 2138*91f16700Schasinglulu #define R12_APXGPT1_EVENT_B (1U << 4) 2139*91f16700Schasinglulu #define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) 2140*91f16700Schasinglulu #define R12_EINT_EVENT_B (1U << 6) 2141*91f16700Schasinglulu #define R12_CONN_WDT_IRQ_B (1U << 7) 2142*91f16700Schasinglulu #define R12_CCIF0_EVENT_B (1U << 8) 2143*91f16700Schasinglulu #define R12_LOWBATTERY_IRQ_B (1U << 9) 2144*91f16700Schasinglulu #define R12_SSPM_SPM_IRQ_B (1U << 10) 2145*91f16700Schasinglulu #define R12_SCP_SPM_IRQ_B (1U << 11) 2146*91f16700Schasinglulu #define R12_SCP_WDT_EVENT_B (1U << 12) 2147*91f16700Schasinglulu #define R12_PCM_WDT_WAKEUP_B (1U << 13) 2148*91f16700Schasinglulu #define R12_USB_CDSC_B (1U << 14) 2149*91f16700Schasinglulu #define R12_USB_POWERDWN_B (1U << 15) 2150*91f16700Schasinglulu #define R12_SYS_TIMER_EVENT_B (1U << 16) 2151*91f16700Schasinglulu #define R12_EINT_EVENT_SECURE_B (1U << 17) 2152*91f16700Schasinglulu #define R12_CCIF1_EVENT_B (1U << 18) 2153*91f16700Schasinglulu #define R12_UART0_IRQ_B (1U << 19) 2154*91f16700Schasinglulu #define R12_AFE_IRQ_MCU_B (1U << 20) 2155*91f16700Schasinglulu #define R12_THERM_CTRL_EVENT_B (1U << 21) 2156*91f16700Schasinglulu #define R12_SYS_CIRQ_IRQ_B (1U << 22) 2157*91f16700Schasinglulu #define R12_MD2AP_PEER_EVENT_B (1U << 23) 2158*91f16700Schasinglulu #define R12_CSYSPWREQ_B (1U << 24) 2159*91f16700Schasinglulu #define R12_MD1_WDT_B (1U << 25) 2160*91f16700Schasinglulu #define R12_CLDMA_EVENT_B (1U << 26) 2161*91f16700Schasinglulu #define R12_SEJ_WDT_GPT_B (1U << 27) 2162*91f16700Schasinglulu #define R12_ALL_SSPM_WAKEUP_B (1U << 28) 2163*91f16700Schasinglulu #define R12_CPU_IRQ_B (1U << 29) 2164*91f16700Schasinglulu #define R12_CPU_WFI_AND_B (1U << 30) 2165*91f16700Schasinglulu #define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) 2166*91f16700Schasinglulu 2167*91f16700Schasinglulu /* --- R12ext Define --- */ 2168*91f16700Schasinglulu #define R12EXT_26M_WAKE (1U << 0) 2169*91f16700Schasinglulu #define R12EXT_26M_SLEEP (1U << 1) 2170*91f16700Schasinglulu #define R12EXT_INFRA_WAKE (1U << 2) 2171*91f16700Schasinglulu #define R12EXT_INFRA_SLEEP (1U << 3) 2172*91f16700Schasinglulu #define R12EXT_APSRC_WAKE (1U << 4) 2173*91f16700Schasinglulu #define R12EXT_APSRC_SLEEP (1U << 5) 2174*91f16700Schasinglulu #define R12EXT_VRF18_WAKE (1U << 6) 2175*91f16700Schasinglulu #define R12EXT_VRF18_SLEEP (1U << 7) 2176*91f16700Schasinglulu #define R12EXT_DVFS_ALL_STATE (1U << 8) 2177*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) 2178*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) 2179*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) 2180*91f16700Schasinglulu #define R12EXT_DDREN_WAKE (1U << 12) 2181*91f16700Schasinglulu #define R12EXT_DDREN_SLEEP (1U << 13) 2182*91f16700Schasinglulu #define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) 2183*91f16700Schasinglulu #define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) 2184*91f16700Schasinglulu #define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) 2185*91f16700Schasinglulu #define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) 2186*91f16700Schasinglulu #define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) 2187*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) 2188*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) 2189*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) 2190*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) 2191*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) 2192*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) 2193*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) 2194*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) 2195*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) 2196*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) 2197*91f16700Schasinglulu #define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) 2198*91f16700Schasinglulu #define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) 2199*91f16700Schasinglulu #define R12EXT_HYBRID_DDREN_WAKE (1U << 31) 2200*91f16700Schasinglulu 2201*91f16700Schasinglulu /* --- R13 Define --- */ 2202*91f16700Schasinglulu #define R13_EXT_SRCCLKENI_0 (1U << 0) 2203*91f16700Schasinglulu #define R13_EXT_SRCCLKENI_1 (1U << 1) 2204*91f16700Schasinglulu #define R13_MD1_SRCCLKENA (1U << 2) 2205*91f16700Schasinglulu #define R13_MD1_APSRC_REQ (1U << 3) 2206*91f16700Schasinglulu #define R13_CONN_DDR_EN (1U << 4) 2207*91f16700Schasinglulu #define R13_MD2_SRCCLKENA (1U << 5) 2208*91f16700Schasinglulu #define R13_SSPM_SRCCLKENA (1U << 6) 2209*91f16700Schasinglulu #define R13_SSPM_APSRC_REQ (1U << 7) 2210*91f16700Schasinglulu #define R13_MD_STATE (1U << 8) 2211*91f16700Schasinglulu #define R13_EMI_CLK_OFF_2_ACK (1U << 9) 2212*91f16700Schasinglulu #define R13_MM_STATE (1U << 10) 2213*91f16700Schasinglulu #define R13_SSPM_STATE (1U << 11) 2214*91f16700Schasinglulu #define R13_MD_DDR_EN (1U << 12) 2215*91f16700Schasinglulu #define R13_CONN_STATE (1U << 13) 2216*91f16700Schasinglulu #define R13_CONN_SRCCLKENA (1U << 14) 2217*91f16700Schasinglulu #define R13_CONN_APSRC_REQ (1U << 15) 2218*91f16700Schasinglulu #define R13_SLEEP_EVENT_STA (1U << 16) 2219*91f16700Schasinglulu #define R13_WAKE_EVENT_STA (1U << 17) 2220*91f16700Schasinglulu #define R13_EMI_IDLE (1U << 18) 2221*91f16700Schasinglulu #define R13_CSYSPWRUPREQ (1U << 19) 2222*91f16700Schasinglulu #define R13_PWRAP_SLEEP_ACK (1U << 20) 2223*91f16700Schasinglulu #define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) 2224*91f16700Schasinglulu #define R13_TOP_MAS_PAU_ACK (1U << 22) 2225*91f16700Schasinglulu #define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) 2226*91f16700Schasinglulu #define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) 2227*91f16700Schasinglulu #define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) 2228*91f16700Schasinglulu #define R13_INFRA_AUX_IDLE (1U << 26) 2229*91f16700Schasinglulu #define R13_DVFS_ALL_STATE (1U << 27) 2230*91f16700Schasinglulu #define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) 2231*91f16700Schasinglulu #define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) 2232*91f16700Schasinglulu #define R13_MD1_VRF18_REQ (1U << 30) 2233*91f16700Schasinglulu #define R13_C2K_VRF18_REQ (1U << 31) 2234*91f16700Schasinglulu 2235*91f16700Schasinglulu #define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) 2236*91f16700Schasinglulu #define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) 2237*91f16700Schasinglulu #define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) 2238*91f16700Schasinglulu 2239*91f16700Schasinglulu #define MP0_SPMC_SRAM_DORMANT_EN (1<<0) 2240*91f16700Schasinglulu #define MP1_SPMC_SRAM_DORMANT_EN (1<<1) 2241*91f16700Schasinglulu #define MP2_SPMC_SRAM_DORMANT_EN (1<<2) 2242*91f16700Schasinglulu 2243*91f16700Schasinglulu #define EVENT_VEC(event, resume, imme, pc) \ 2244*91f16700Schasinglulu (((pc) << 16) | \ 2245*91f16700Schasinglulu (!!(imme) << 7) | \ 2246*91f16700Schasinglulu (!!(resume) << 6) | \ 2247*91f16700Schasinglulu ((event) & 0x3f)) 2248*91f16700Schasinglulu 2249*91f16700Schasinglulu #define SPM_PROJECT_CODE 0xb16 2250*91f16700Schasinglulu #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2251*91f16700Schasinglulu 2252*91f16700Schasinglulu /************************************** 2253*91f16700Schasinglulu * Config and Parameter 2254*91f16700Schasinglulu **************************************/ 2255*91f16700Schasinglulu #define POWER_ON_VAL1_DEF 0x00015800 2256*91f16700Schasinglulu #define PCM_FSM_STA_DEF 0x00108490 2257*91f16700Schasinglulu #define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 2258*91f16700Schasinglulu #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 2259*91f16700Schasinglulu #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) 2260*91f16700Schasinglulu 2261*91f16700Schasinglulu /************************************** 2262*91f16700Schasinglulu * Define and Declare 2263*91f16700Schasinglulu **************************************/ 2264*91f16700Schasinglulu /* PCM_PWR_IO_EN */ 2265*91f16700Schasinglulu #define PCM_PWRIO_EN_R0 (1U << 0) 2266*91f16700Schasinglulu #define PCM_PWRIO_EN_R7 (1U << 7) 2267*91f16700Schasinglulu #define PCM_RF_SYNC_R0 (1U << 16) 2268*91f16700Schasinglulu #define PCM_RF_SYNC_R6 (1U << 22) 2269*91f16700Schasinglulu #define PCM_RF_SYNC_R7 (1U << 23) 2270*91f16700Schasinglulu 2271*91f16700Schasinglulu /* SPM_SWINT */ 2272*91f16700Schasinglulu #define PCM_SW_INT0 (1U << 0) 2273*91f16700Schasinglulu #define PCM_SW_INT1 (1U << 1) 2274*91f16700Schasinglulu #define PCM_SW_INT2 (1U << 2) 2275*91f16700Schasinglulu #define PCM_SW_INT3 (1U << 3) 2276*91f16700Schasinglulu #define PCM_SW_INT4 (1U << 4) 2277*91f16700Schasinglulu #define PCM_SW_INT5 (1U << 5) 2278*91f16700Schasinglulu #define PCM_SW_INT6 (1U << 6) 2279*91f16700Schasinglulu #define PCM_SW_INT7 (1U << 7) 2280*91f16700Schasinglulu #define PCM_SW_INT8 (1U << 8) 2281*91f16700Schasinglulu #define PCM_SW_INT9 (1U << 9) 2282*91f16700Schasinglulu #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ 2283*91f16700Schasinglulu PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ 2284*91f16700Schasinglulu PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ 2285*91f16700Schasinglulu PCM_SW_INT0) 2286*91f16700Schasinglulu /* SPM_IRQ_MASK */ 2287*91f16700Schasinglulu #define ISRM_TWAM (1U << 2) 2288*91f16700Schasinglulu #define ISRM_PCM_RETURN (1U << 3) 2289*91f16700Schasinglulu #define ISRM_RET_IRQ0 (1U << 8) 2290*91f16700Schasinglulu #define ISRM_RET_IRQ1 (1U << 9) 2291*91f16700Schasinglulu #define ISRM_RET_IRQ2 (1U << 10) 2292*91f16700Schasinglulu #define ISRM_RET_IRQ3 (1U << 11) 2293*91f16700Schasinglulu #define ISRM_RET_IRQ4 (1U << 12) 2294*91f16700Schasinglulu #define ISRM_RET_IRQ5 (1U << 13) 2295*91f16700Schasinglulu #define ISRM_RET_IRQ6 (1U << 14) 2296*91f16700Schasinglulu #define ISRM_RET_IRQ7 (1U << 15) 2297*91f16700Schasinglulu #define ISRM_RET_IRQ8 (1U << 16) 2298*91f16700Schasinglulu #define ISRM_RET_IRQ9 (1U << 17) 2299*91f16700Schasinglulu #define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ 2300*91f16700Schasinglulu ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ 2301*91f16700Schasinglulu ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ 2302*91f16700Schasinglulu ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ 2303*91f16700Schasinglulu ISRM_RET_IRQ1) 2304*91f16700Schasinglulu #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) 2305*91f16700Schasinglulu #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 2306*91f16700Schasinglulu 2307*91f16700Schasinglulu /* SPM_IRQ_STA */ 2308*91f16700Schasinglulu #define ISRS_TWAM (1U << 2) 2309*91f16700Schasinglulu #define ISRS_PCM_RETURN (1U << 3) 2310*91f16700Schasinglulu #define ISRS_SW_INT0 (1U << 4) 2311*91f16700Schasinglulu #define ISRC_TWAM ISRS_TWAM 2312*91f16700Schasinglulu #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN 2313*91f16700Schasinglulu #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 2314*91f16700Schasinglulu 2315*91f16700Schasinglulu /* SPM_WAKEUP_MISC */ 2316*91f16700Schasinglulu #define WAKE_MISC_TWAM (1U << 18) 2317*91f16700Schasinglulu #define WAKE_MISC_PCM_TIMER (1U << 19) 2318*91f16700Schasinglulu #define WAKE_MISC_CPU_WAKE (1U << 20) 2319*91f16700Schasinglulu 2320*91f16700Schasinglulu enum SPM_WAKE_SRC_LIST { 2321*91f16700Schasinglulu WAKE_SRC_R12_PCM_TIMER = (1U << 0), 2322*91f16700Schasinglulu WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), 2323*91f16700Schasinglulu WAKE_SRC_R12_KP_IRQ_B = (1U << 2), 2324*91f16700Schasinglulu WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), 2325*91f16700Schasinglulu WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), 2326*91f16700Schasinglulu WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), 2327*91f16700Schasinglulu WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), 2328*91f16700Schasinglulu WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), 2329*91f16700Schasinglulu WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), 2330*91f16700Schasinglulu WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), 2331*91f16700Schasinglulu WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), 2332*91f16700Schasinglulu WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), 2333*91f16700Schasinglulu WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), 2334*91f16700Schasinglulu WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), 2335*91f16700Schasinglulu WAKE_SRC_R12_USB_CDSC_B = (1U << 14), 2336*91f16700Schasinglulu WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), 2337*91f16700Schasinglulu WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), 2338*91f16700Schasinglulu WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), 2339*91f16700Schasinglulu WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), 2340*91f16700Schasinglulu WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), 2341*91f16700Schasinglulu WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), 2342*91f16700Schasinglulu WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), 2343*91f16700Schasinglulu WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), 2344*91f16700Schasinglulu WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), 2345*91f16700Schasinglulu WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), 2346*91f16700Schasinglulu WAKE_SRC_R12_MD1_WDT_B = (1U << 25), 2347*91f16700Schasinglulu WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), 2348*91f16700Schasinglulu WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), 2349*91f16700Schasinglulu WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), 2350*91f16700Schasinglulu WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), 2351*91f16700Schasinglulu WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), 2352*91f16700Schasinglulu }; 2353*91f16700Schasinglulu 2354*91f16700Schasinglulu struct pcm_desc { 2355*91f16700Schasinglulu const char *version; 2356*91f16700Schasinglulu const uint32_t *base; 2357*91f16700Schasinglulu const uint32_t base_dma; 2358*91f16700Schasinglulu const uint32_t size; 2359*91f16700Schasinglulu const uint32_t sess; 2360*91f16700Schasinglulu const uint32_t replace; 2361*91f16700Schasinglulu const uint32_t addr_2nd; 2362*91f16700Schasinglulu const uint32_t reserved; 2363*91f16700Schasinglulu 2364*91f16700Schasinglulu uint32_t vec0; 2365*91f16700Schasinglulu uint32_t vec1; 2366*91f16700Schasinglulu uint32_t vec2; 2367*91f16700Schasinglulu uint32_t vec3; 2368*91f16700Schasinglulu uint32_t vec4; 2369*91f16700Schasinglulu uint32_t vec5; 2370*91f16700Schasinglulu uint32_t vec6; 2371*91f16700Schasinglulu uint32_t vec7; 2372*91f16700Schasinglulu uint32_t vec8; 2373*91f16700Schasinglulu uint32_t vec9; 2374*91f16700Schasinglulu uint32_t vec10; 2375*91f16700Schasinglulu uint32_t vec11; 2376*91f16700Schasinglulu uint32_t vec12; 2377*91f16700Schasinglulu uint32_t vec13; 2378*91f16700Schasinglulu uint32_t vec14; 2379*91f16700Schasinglulu uint32_t vec15; 2380*91f16700Schasinglulu }; 2381*91f16700Schasinglulu 2382*91f16700Schasinglulu struct pwr_ctrl { 2383*91f16700Schasinglulu uint32_t pcm_flags; 2384*91f16700Schasinglulu uint32_t pcm_flags1; 2385*91f16700Schasinglulu uint32_t timer_val; 2386*91f16700Schasinglulu uint32_t wake_src; 2387*91f16700Schasinglulu 2388*91f16700Schasinglulu /* SPM_AP_STANDBY_CON */ 2389*91f16700Schasinglulu uint8_t wfi_op; 2390*91f16700Schasinglulu uint8_t mp0_cputop_idle_mask; 2391*91f16700Schasinglulu uint8_t mp1_cputop_idle_mask; 2392*91f16700Schasinglulu uint8_t mcusys_idle_mask; 2393*91f16700Schasinglulu uint8_t mm_mask_b; 2394*91f16700Schasinglulu uint8_t md_ddr_en_0_dbc_en; 2395*91f16700Schasinglulu uint8_t md_ddr_en_1_dbc_en; 2396*91f16700Schasinglulu uint8_t md_mask_b; 2397*91f16700Schasinglulu uint8_t sspm_mask_b; 2398*91f16700Schasinglulu uint8_t scp_mask_b; 2399*91f16700Schasinglulu uint8_t srcclkeni_mask_b; 2400*91f16700Schasinglulu uint8_t md_apsrc_1_sel; 2401*91f16700Schasinglulu uint8_t md_apsrc_0_sel; 2402*91f16700Schasinglulu uint8_t conn_ddr_en_dbc_en; 2403*91f16700Schasinglulu uint8_t conn_mask_b; 2404*91f16700Schasinglulu uint8_t conn_apsrc_sel; 2405*91f16700Schasinglulu 2406*91f16700Schasinglulu /* SPM_SRC_REQ */ 2407*91f16700Schasinglulu uint8_t spm_apsrc_req; 2408*91f16700Schasinglulu uint8_t spm_f26m_req; 2409*91f16700Schasinglulu uint8_t spm_infra_req; 2410*91f16700Schasinglulu uint8_t spm_vrf18_req; 2411*91f16700Schasinglulu uint8_t spm_ddren_req; 2412*91f16700Schasinglulu uint8_t spm_rsv_src_req; 2413*91f16700Schasinglulu uint8_t spm_ddren_2_req; 2414*91f16700Schasinglulu uint8_t cpu_md_dvfs_sop_force_on; 2415*91f16700Schasinglulu 2416*91f16700Schasinglulu /* SPM_SRC_MASK */ 2417*91f16700Schasinglulu uint8_t csyspwreq_mask; 2418*91f16700Schasinglulu uint8_t ccif0_md_event_mask_b; 2419*91f16700Schasinglulu uint8_t ccif0_ap_event_mask_b; 2420*91f16700Schasinglulu uint8_t ccif1_md_event_mask_b; 2421*91f16700Schasinglulu uint8_t ccif1_ap_event_mask_b; 2422*91f16700Schasinglulu uint8_t ccif2_md_event_mask_b; 2423*91f16700Schasinglulu uint8_t ccif2_ap_event_mask_b; 2424*91f16700Schasinglulu uint8_t ccif3_md_event_mask_b; 2425*91f16700Schasinglulu uint8_t ccif3_ap_event_mask_b; 2426*91f16700Schasinglulu uint8_t md_srcclkena_0_infra_mask_b; 2427*91f16700Schasinglulu uint8_t md_srcclkena_1_infra_mask_b; 2428*91f16700Schasinglulu uint8_t conn_srcclkena_infra_mask_b; 2429*91f16700Schasinglulu uint8_t ufs_infra_req_mask_b; 2430*91f16700Schasinglulu uint8_t srcclkeni_infra_mask_b; 2431*91f16700Schasinglulu uint8_t md_apsrc_req_0_infra_mask_b; 2432*91f16700Schasinglulu uint8_t md_apsrc_req_1_infra_mask_b; 2433*91f16700Schasinglulu uint8_t conn_apsrcreq_infra_mask_b; 2434*91f16700Schasinglulu uint8_t ufs_srcclkena_mask_b; 2435*91f16700Schasinglulu uint8_t md_vrf18_req_0_mask_b; 2436*91f16700Schasinglulu uint8_t md_vrf18_req_1_mask_b; 2437*91f16700Schasinglulu uint8_t ufs_vrf18_req_mask_b; 2438*91f16700Schasinglulu uint8_t gce_vrf18_req_mask_b; 2439*91f16700Schasinglulu uint8_t conn_infra_req_mask_b; 2440*91f16700Schasinglulu uint8_t gce_apsrc_req_mask_b; 2441*91f16700Schasinglulu uint8_t disp0_apsrc_req_mask_b; 2442*91f16700Schasinglulu uint8_t disp1_apsrc_req_mask_b; 2443*91f16700Schasinglulu uint8_t mfg_req_mask_b; 2444*91f16700Schasinglulu uint8_t vdec_req_mask_b; 2445*91f16700Schasinglulu 2446*91f16700Schasinglulu /* SPM_SRC2_MASK */ 2447*91f16700Schasinglulu uint8_t md_ddr_en_0_mask_b; 2448*91f16700Schasinglulu uint8_t md_ddr_en_1_mask_b; 2449*91f16700Schasinglulu uint8_t conn_ddr_en_mask_b; 2450*91f16700Schasinglulu uint8_t ddren_sspm_apsrc_req_mask_b; 2451*91f16700Schasinglulu uint8_t ddren_scp_apsrc_req_mask_b; 2452*91f16700Schasinglulu uint8_t disp0_ddren_mask_b; 2453*91f16700Schasinglulu uint8_t disp1_ddren_mask_b; 2454*91f16700Schasinglulu uint8_t gce_ddren_mask_b; 2455*91f16700Schasinglulu uint8_t ddren_emi_self_refresh_ch0_mask_b; 2456*91f16700Schasinglulu uint8_t ddren_emi_self_refresh_ch1_mask_b; 2457*91f16700Schasinglulu 2458*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_MASK */ 2459*91f16700Schasinglulu uint32_t spm_wakeup_event_mask; 2460*91f16700Schasinglulu 2461*91f16700Schasinglulu /* SPM_WAKEUP_EVENT_EXT_MASK */ 2462*91f16700Schasinglulu uint32_t spm_wakeup_event_ext_mask; 2463*91f16700Schasinglulu 2464*91f16700Schasinglulu /* SPM_SRC3_MASK */ 2465*91f16700Schasinglulu uint8_t md_ddr_en_2_0_mask_b; 2466*91f16700Schasinglulu uint8_t md_ddr_en_2_1_mask_b; 2467*91f16700Schasinglulu uint8_t conn_ddr_en_2_mask_b; 2468*91f16700Schasinglulu uint8_t ddren2_sspm_apsrc_req_mask_b; 2469*91f16700Schasinglulu uint8_t ddren2_scp_apsrc_req_mask_b; 2470*91f16700Schasinglulu uint8_t disp0_ddren2_mask_b; 2471*91f16700Schasinglulu uint8_t disp1_ddren2_mask_b; 2472*91f16700Schasinglulu uint8_t gce_ddren2_mask_b; 2473*91f16700Schasinglulu uint8_t ddren2_emi_self_refresh_ch0_mask_b; 2474*91f16700Schasinglulu uint8_t ddren2_emi_self_refresh_ch1_mask_b; 2475*91f16700Schasinglulu 2476*91f16700Schasinglulu uint8_t mp0_cpu0_wfi_en; 2477*91f16700Schasinglulu uint8_t mp0_cpu1_wfi_en; 2478*91f16700Schasinglulu uint8_t mp0_cpu2_wfi_en; 2479*91f16700Schasinglulu uint8_t mp0_cpu3_wfi_en; 2480*91f16700Schasinglulu 2481*91f16700Schasinglulu uint8_t mp1_cpu0_wfi_en; 2482*91f16700Schasinglulu uint8_t mp1_cpu1_wfi_en; 2483*91f16700Schasinglulu uint8_t mp1_cpu2_wfi_en; 2484*91f16700Schasinglulu uint8_t mp1_cpu3_wfi_en; 2485*91f16700Schasinglulu }; 2486*91f16700Schasinglulu 2487*91f16700Schasinglulu struct wake_status { 2488*91f16700Schasinglulu uint32_t assert_pc; 2489*91f16700Schasinglulu uint32_t r12; 2490*91f16700Schasinglulu uint32_t r12_ext; 2491*91f16700Schasinglulu uint32_t raw_sta; 2492*91f16700Schasinglulu uint32_t raw_ext_sta; 2493*91f16700Schasinglulu uint32_t wake_misc; 2494*91f16700Schasinglulu uint32_t timer_out; 2495*91f16700Schasinglulu uint32_t r13; 2496*91f16700Schasinglulu uint32_t r15; 2497*91f16700Schasinglulu uint32_t idle_sta; 2498*91f16700Schasinglulu uint32_t req_sta; 2499*91f16700Schasinglulu uint32_t debug_flag; 2500*91f16700Schasinglulu uint32_t debug_flag1; 2501*91f16700Schasinglulu uint32_t event_reg; 2502*91f16700Schasinglulu uint32_t isr; 2503*91f16700Schasinglulu uint32_t sw_flag; 2504*91f16700Schasinglulu uint32_t sw_flag1; 2505*91f16700Schasinglulu uint32_t log_index; 2506*91f16700Schasinglulu }; 2507*91f16700Schasinglulu 2508*91f16700Schasinglulu typedef struct spm_data { 2509*91f16700Schasinglulu unsigned int cmd; 2510*91f16700Schasinglulu union { 2511*91f16700Schasinglulu struct { 2512*91f16700Schasinglulu unsigned int sys_timestamp_l; 2513*91f16700Schasinglulu unsigned int sys_timestamp_h; 2514*91f16700Schasinglulu unsigned int sys_src_clk_l; 2515*91f16700Schasinglulu unsigned int sys_src_clk_h; 2516*91f16700Schasinglulu unsigned int spm_opt; 2517*91f16700Schasinglulu } suspend; 2518*91f16700Schasinglulu struct { 2519*91f16700Schasinglulu unsigned int args1; 2520*91f16700Schasinglulu unsigned int args2; 2521*91f16700Schasinglulu unsigned int args3; 2522*91f16700Schasinglulu unsigned int args4; 2523*91f16700Schasinglulu unsigned int args5; 2524*91f16700Schasinglulu unsigned int args6; 2525*91f16700Schasinglulu unsigned int args7; 2526*91f16700Schasinglulu } args; 2527*91f16700Schasinglulu } u; 2528*91f16700Schasinglulu } spm_data_t; 2529*91f16700Schasinglulu 2530*91f16700Schasinglulu enum { 2531*91f16700Schasinglulu SPM_SUSPEND, 2532*91f16700Schasinglulu SPM_RESUME 2533*91f16700Schasinglulu }; 2534*91f16700Schasinglulu 2535*91f16700Schasinglulu extern void spm_disable_pcm_timer(void); 2536*91f16700Schasinglulu extern void spm_set_bootaddr(unsigned long bootaddr); 2537*91f16700Schasinglulu extern void spm_set_cpu_status(int cpu); 2538*91f16700Schasinglulu extern void spm_set_power_control(const struct pwr_ctrl *pwrctrl); 2539*91f16700Schasinglulu extern void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 2540*91f16700Schasinglulu extern void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); 2541*91f16700Schasinglulu extern void spm_send_cpu_wakeup_event(void); 2542*91f16700Schasinglulu extern void spm_get_wakeup_status(struct wake_status *wakesta); 2543*91f16700Schasinglulu extern void spm_clean_after_wakeup(void); 2544*91f16700Schasinglulu extern void spm_output_wake_reason(struct wake_status *wakesta, 2545*91f16700Schasinglulu const char *scenario); 2546*91f16700Schasinglulu extern void spm_set_pcm_wdt(int en); 2547*91f16700Schasinglulu extern void spm_lock_get(void); 2548*91f16700Schasinglulu extern void spm_lock_release(void); 2549*91f16700Schasinglulu extern void spm_boot_init(void); 2550*91f16700Schasinglulu extern const char *spm_get_firmware_version(void); 2551*91f16700Schasinglulu 2552*91f16700Schasinglulu #endif /* SPM_H */ 2553