1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PMIC_WRAP_INIT_H 8*91f16700Schasinglulu #define PMIC_WRAP_INIT_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <platform_def.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* external API */ 14*91f16700Schasinglulu int32_t pwrap_read(uint32_t adr, uint32_t *rdata); 15*91f16700Schasinglulu int32_t pwrap_write(uint32_t adr, uint32_t wdata); 16*91f16700Schasinglulu 17*91f16700Schasinglulu static struct mt8183_pmic_wrap_regs *const mtk_pwrap = 18*91f16700Schasinglulu (void *)PMIC_WRAP_BASE; 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* timeout setting */ 21*91f16700Schasinglulu enum { 22*91f16700Schasinglulu TIMEOUT_READ = 255, /* us */ 23*91f16700Schasinglulu TIMEOUT_WAIT_IDLE = 255 /* us */ 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* PMIC_WRAP registers */ 27*91f16700Schasinglulu struct mt8183_pmic_wrap_regs { 28*91f16700Schasinglulu uint32_t reserved[776]; 29*91f16700Schasinglulu uint32_t wacs2_cmd; 30*91f16700Schasinglulu uint32_t wacs2_rdata; 31*91f16700Schasinglulu uint32_t wacs2_vldclr; 32*91f16700Schasinglulu uint32_t reserved1[4]; 33*91f16700Schasinglulu }; 34*91f16700Schasinglulu 35*91f16700Schasinglulu enum { 36*91f16700Schasinglulu RDATA_WACS_RDATA_SHIFT = 0, 37*91f16700Schasinglulu RDATA_WACS_FSM_SHIFT = 16, 38*91f16700Schasinglulu RDATA_WACS_REQ_SHIFT = 19, 39*91f16700Schasinglulu RDATA_SYNC_IDLE_SHIFT, 40*91f16700Schasinglulu RDATA_INIT_DONE_SHIFT, 41*91f16700Schasinglulu RDATA_SYS_IDLE_SHIFT, 42*91f16700Schasinglulu }; 43*91f16700Schasinglulu 44*91f16700Schasinglulu enum { 45*91f16700Schasinglulu RDATA_WACS_RDATA_MASK = 0xffff, 46*91f16700Schasinglulu RDATA_WACS_FSM_MASK = 0x7, 47*91f16700Schasinglulu RDATA_WACS_REQ_MASK = 0x1, 48*91f16700Schasinglulu RDATA_SYNC_IDLE_MASK = 0x1, 49*91f16700Schasinglulu RDATA_INIT_DONE_MASK = 0x1, 50*91f16700Schasinglulu RDATA_SYS_IDLE_MASK = 0x1, 51*91f16700Schasinglulu }; 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* WACS_FSM */ 54*91f16700Schasinglulu enum { 55*91f16700Schasinglulu WACS_FSM_IDLE = 0x00, 56*91f16700Schasinglulu WACS_FSM_REQ = 0x02, 57*91f16700Schasinglulu WACS_FSM_WFDLE = 0x04, 58*91f16700Schasinglulu WACS_FSM_WFVLDCLR = 0x06, 59*91f16700Schasinglulu WACS_INIT_DONE = 0x01, 60*91f16700Schasinglulu WACS_SYNC_IDLE = 0x01, 61*91f16700Schasinglulu WACS_SYNC_BUSY = 0x00 62*91f16700Schasinglulu }; 63*91f16700Schasinglulu 64*91f16700Schasinglulu /* error information flag */ 65*91f16700Schasinglulu enum { 66*91f16700Schasinglulu E_PWR_INVALID_ARG = 1, 67*91f16700Schasinglulu E_PWR_INVALID_RW = 2, 68*91f16700Schasinglulu E_PWR_INVALID_ADDR = 3, 69*91f16700Schasinglulu E_PWR_INVALID_WDAT = 4, 70*91f16700Schasinglulu E_PWR_INVALID_OP_MANUAL = 5, 71*91f16700Schasinglulu E_PWR_NOT_IDLE_STATE = 6, 72*91f16700Schasinglulu E_PWR_NOT_INIT_DONE = 7, 73*91f16700Schasinglulu E_PWR_NOT_INIT_DONE_READ = 8, 74*91f16700Schasinglulu E_PWR_WAIT_IDLE_TIMEOUT = 9, 75*91f16700Schasinglulu E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, 76*91f16700Schasinglulu E_PWR_INIT_SIDLY_FAIL = 11, 77*91f16700Schasinglulu E_PWR_RESET_TIMEOUT = 12, 78*91f16700Schasinglulu E_PWR_TIMEOUT = 13, 79*91f16700Schasinglulu E_PWR_INIT_RESET_SPI = 20, 80*91f16700Schasinglulu E_PWR_INIT_SIDLY = 21, 81*91f16700Schasinglulu E_PWR_INIT_REG_CLOCK = 22, 82*91f16700Schasinglulu E_PWR_INIT_ENABLE_PMIC = 23, 83*91f16700Schasinglulu E_PWR_INIT_DIO = 24, 84*91f16700Schasinglulu E_PWR_INIT_CIPHER = 25, 85*91f16700Schasinglulu E_PWR_INIT_WRITE_TEST = 26, 86*91f16700Schasinglulu E_PWR_INIT_ENABLE_CRC = 27, 87*91f16700Schasinglulu E_PWR_INIT_ENABLE_DEWRAP = 28, 88*91f16700Schasinglulu E_PWR_INIT_ENABLE_EVENT = 29, 89*91f16700Schasinglulu E_PWR_READ_TEST_FAIL = 30, 90*91f16700Schasinglulu E_PWR_WRITE_TEST_FAIL = 31, 91*91f16700Schasinglulu E_PWR_SWITCH_DIO = 32 92*91f16700Schasinglulu }; 93*91f16700Schasinglulu 94*91f16700Schasinglulu #endif /* PMIC_WRAP_INIT_H */ 95